SN74LVC1 Search Results

Contextual Info: SN74LVC137 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES SCAS340 - MARCH 1994 » EPIC Enhanced-Performance Implanted CMOS Submicron Process • Typical V o lp (Output Ground Bounce) D, DB, OR PW PACKAGE (TOP VIEW) A[ B[ c[ Ü2A [ S2B[ G1[

Contextual Info: SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS 3CAS317A- NOVEMBER 1993 - REVISED OCTOBER 199S | • Member of the Texas Instruments Wldobua Family • EP/C™ Enhanced-Performance Implanted CMOS Submicron Process • Typical V q l p (Output Ground Bounce)

Contextual Info: I SN74LVC158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER SCAS342 - MARCH 1994 D, DB, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

SN74LVC16544

Contextual Info: SN74LVC16544 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS351 - MARCH 1994 Member of the Texas Instruments Wldebus Family EPIC™ Enhanced-Performance Implanted CMOS Submicron Process DGG OR DL PACKAGE ftOP VIEW) 1ÜÊÂB[ 1 Typical V q l p (Output Ground Bounce)

SN74LVC16245

Contextual Info: SN74LVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS I SCAS314 - NOVEMBER 1993 - REVISED MARCH 1994 DGG OR DL PACKAGE TOP VIEW Member of the Texas Instruments Wldebus Family EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process E 1DIR ,

Contextual Info: SN74LVC16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS320 - NOVEMBER 1993 - REVISED MARCH 1994 Member of the Texas Instruments Wldebus Family DOG OR DL PACKAGE TOP VIEW EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process 10EA B L 1

Contextual Info: SN74LVC157 QUADRUPLE 2-LINE TO 1-UNE DATA SELECTOR/MULTIPLEXER SCAS292B-JANUARY 19 9 3 - REVISED JULY 1995 I • EPIC Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model

Contextual Info: SN74LVC16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS312 - NOVEMBER 1993 - REVISED MARCH 1994 Member of the Texas Instruments Wldebus Family EPIC™ Enhanced-Performance Implanted CMOS Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C

SN74LVC162244

Contextual Info: SN74LVC162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS I SCAS546 - OCTOBER 1995 10Ê 1Y1 1Y2 GND 1Y3 1Y4 Output Ports Have Equivalent 26-Q Series Resistors, So No External Resistors Are Required Typical V q l p Output Ground Bounce < 0.8 V at Vc c = 3.3 V, TA = 25°C

Contextual Info: SN74LVC16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS 3CES081A - DECEMBER 1 9 95 - REVISED JANUARY 1998 DQQ OR DL PACKAOE TOP VIEW Member of the Texas Instruments Wldebus Family EP/C™ (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce)

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339H – MARCH 1994 – REVISED OCTOBER 1998 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

Contextual Info: SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT SCES295D – JUNE 2000 – REVISED DECEMBER 2000 D D D D DBV OR DCK PACKAGE TOP VIEW Supports 5-V VCC Operation Input and Open-Drain Output Accept Voltages up to 5.5 V Latch-Up Performance Exceeds 100 mA Per

Contextual Info: SN74LVC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCES221D – APRIL 1999 – REVISED JANUARY 2001 D D D D DBV OR DCK PACKAGE TOP VIEW Supports 5-V VCC Operation Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per

c07f

Abstract: MARKING C07F marking C075
Contextual Info: SN74LVC1G07 www.ti.com SCES296AA – FEBRUARY 2000 – REVISED JULY 2013 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT Check for Samples: SN74LVC1G07 FEATURES DESCRIPTION • This single buffer/driver is designed for 1.65-V to 5.5V VCC operation. 1 2 • •

Contextual Info: SN74LVC1G332 www.ti.com SCES489E – SEPTEMBER 2003 – REVISED DECEMBER 2013 Single 3-Input Positive-OR Gate Check for Samples: SN74LVC1G332 FEATURES DESCRIPTION • The SN74LVC1G332 device performs the Boolean Y + A B ) C or Y + A • B • C function

Contextual Info: SN74LVC1G126 SINGLE BUS BUFFER GATE WITH 3ĆSTATE OUTPUT SCES224M − APRIL 1999 − REVISED JUNE 2005 D Available in the Texas Instruments D D D D D DBV PACKAGE TOP VIEW OE D Ioff Supports Partial-Power-Down Mode NanoStar and NanoFree Packages Supports 5-V VCC Operation

Contextual Info: SN74LVC1G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT www.ti.com SCES538A – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • • • • DBV OR DCK PACKAGE TOP VIEW Available in the Texas Instruments NanoStar and NanoFree™ Packages

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

Contextual Info: SN74LVC1G17-EP www.ti.com SGLS336 – APRIL 2006 SINGLE SCHMITT-TRIGGER BUFFER FEATURES • • • • • • • • • • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing

Contextual Info: SN74LVC1G32-EP SINGLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES458A – DECEMBER 2003 – REVISED NOVEMBER 2005 FEATURES • • • • • • • 1 • • • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: www.ti.com SN74LVC16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS FEATURES • • • • • • • Member of the Texas Instruments Widebus Family EPIC™ Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce)

Contextual Info: SN74LVC1G98-Q1 CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES562B – MARCH 2004 – REVISED DECEMBER 2005 FEATURES • • • • • • • • • • 1 Qualification in Accordance With AEC-Q100 (1) Qualified for Automotive Applications Customer-Specific Configuration Control Can

Contextual Info: SN74LVC1G139 2-TO-4 LINE DECODER www.ti.com SCES602B – AUGUST 2004 – REVISED DECEMBER 2005 FEATURES • • • • • • • • Available in the Texas Instruments NanoStar and NanoFree™ Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V

LVC1G86

Contextual Info: SN74LVC1G86 SINGLE 2ĆINPUT EXCLUSIVEĆOR GATE SCES222M − APRIL 1999 − REVISED JUNE 2005 D Available in the Texas Instruments D D D D D DBV PACKAGE TOP VIEW A D Ioff Supports Partial-Power-Down Mode NanoStar and NanoFree Packages Supports 5-V VCC Operation