SSTL STANDARDS Search Results

SSTV16857

Abstract: IDT74SSTV16857 PC2100 PC2700 PC3200 SSTVN16857
Contextual Info: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • 1:1 registered buffer • Meets or exceeds JEDEC standards for SSTV16857 and SSTVN16857 • 2.3V to 2.7V operation for PC1600, PC2100, and PC2700

GTLP16612

Abstract: SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH1645 SN74GTLPH16612 SSTL-3 sstl lvttl Translator
Contextual Info: White Paper Using MAX 7000B Devices to Replace I/O Drivers Introduction The Altera® MAX® 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM memory interfaces.

SSTV16857

Contextual Info: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • 1:1 registered buffer • Meets or exceeds JEDEC standards for SSTV16857 and SSTVN16857 • 2.3V to 2.7V operation for PC1600, PC2100, and PC2700

altera EPM7032B

Abstract: GTLP16612 GTLP16T1655 SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH16612
Contextual Info: Using MAX 7000B Devices to Replace I/O Drivers November 2005, ver. 1.1 Introduction Application Note 293 The Altera MAX® 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM memory interfaces.

SSTV16857

Contextual Info: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • 1:1 registered buffer • Meets or exceeds JEDEC standards for SSTV16857 and SSTVN16857 • 2.3V to 2.7V operation for PC1600, PC2100, and PC2700

SSTV16857

Contextual Info: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • 1:1 registered buffer • Meets or exceeds JEDEC standards for SSTV16857 and SSTVN16857 • 2.3V to 2.7V operation for PC1600, PC2100, and PC2700

Contextual Info: LP2998 LP2998 DDR-I and DDR-II Termination Regulator Literature Number: SNVS521G LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of

LP2994

Abstract: LP2994M LP2994MX M08A
Contextual Info: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

GTLP16612

Abstract: GTLP16T1655 SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH16612
Contextual Info: Using MAX 7000B Devices to Replace I/O Drivers December 2002, ver. 1.0 Introduction Application Note 293 The Altera MAX® 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM memory interfaces.

CMOS applications handbook

Abstract: ttl to mini-lvds CII51010-2 EP2C20 EP2C35 EP2C50 SSTL-18
Contextual Info: 10. Selectable I/O Standards in Cyclone II Devices CII51010-2.4 Introduction The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18, SSTL-2, and

SSTV16857

Abstract: IDT74SSTV16857 PC2100 PC2700 PC3200 SSTVN16857
Contextual Info: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • 1:1 registered buffer • Meets or exceeds JEDEC standards for SSTV16857 and SSTVN16857 • 2.3V to 2.7V operation for PC1600, PC2100, and PC2700

JESD85

Abstract: JESD87 ANSI/TIA/EIA-644 15-V EP1C12 JESD89A
Contextual Info: 8. Using Selectable I/O Standards in Cyclone Devices C51008-1.6 Introduction The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-2, SSTL-3, and

LP2994

Abstract: LP2994M LP2994MX M08A
Contextual Info: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

SSTL-18

Abstract: ttl to mini-lvds CII51010-2 EP2C20 EP2C35 EP2C50 JESD8-15
Contextual Info: 10. Selectable I/O Standards in Cyclone II Devices CII51010-2.3 Introduction The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-18, SSTL-2, and

51a soic8

Contextual Info: LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES DESCRIPTION • • • • • • • The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for

51C SOIC8

Contextual Info: LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES DESCRIPTION • • • • • • • The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for

JESD87

Abstract: AN253
Contextual Info: Using Selectable I/O Standards in Cyclone Devices February 2003, ver. 1.1 Introduction Application Note 253 The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-2, SSTL-3, and

JESD85

Abstract: JESD89A
Contextual Info: Using Selectable I/O Standards in Cyclone Devices September 2002, ver. 1.0 Introduction Application Note 253 The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. Selectable I/O capabilities such as SSTL-2, SSTL-3, and

Contextual Info: OBSOLETE LP2994 www.ti.com SNVS202C – MAY 2002 – REVISED APRIL 2013 DDR Termination Regulator Check for Samples: LP2994 FEATURES DESCRIPTION • • • • • • • The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3

Contextual Info: LP2998 www.ti.com SNVS521I – DECEMBER 2007 – REVISED APRIL 2013 LP2998 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998 FEATURES DESCRIPTION • • • • • • • • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications

2995M

Abstract: "2995m DDA0008A LP2995M 51C SOIC8
Contextual Info: LP2995 www.ti.com SNVS190L – MAY 2004 – REVISED JUNE 2012 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES DESCRIPTION • • • • • • • The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for

LP2995M

Abstract: 2995M 51C SOIC8
Contextual Info: LP2995 www.ti.com SNVS190L – MAY 2004 – REVISED JUNE 2012 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES DESCRIPTION • • • • • • • The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for

Contextual Info: LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 LP2995 DDR Termination Regulator Check for Samples: LP2995 FEATURES DESCRIPTION • • • • • • • The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for

Contextual Info: LP2998/LP2998-Q1 www.ti.com SNVS521J – DECEMBER 2007 – REVISED DECEMBER 2013 LP2998/LP2998-Q1 DDR-I and DDR-II Termination Regulator Check for Samples: LP2998/LP2998-Q1 FEATURES DESCRIPTION • The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications