SUPPORT Search Results

7408, 7404, 7486, 7432

Abstract: RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404
Contextual Info: TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 • Twelve Arrays with up to 26K Available Gates • Fast Prototype Turnaround Time • Extensive Design Support - Design Libraries Compatible with Daisy, Valid, and Mentor CAE Systems - Tl Regional ASIC Design Centers

Contextual Info: TOSHIBA TC55V2325FF-100 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 65,536 W O R D x 32 BIT Synchronous Pipelined Burst SRAM DESCRIPTION The TC55V2325FF is a 2 ,0 9 7 ,1 5 2 bit synchronous pipelined burst SRAM that is organized as 65,536 words by 32 bits and designed for use in a secondary cache to support MPUs which have burst

NCC equivalent

Contextual Info: TMS29F400T, TMS29F400B 524288 BY 8-BIT/262144 BY 16-BIT FLASH M EMORIES • I • Single Power Supply Supports 5 V ± 10% Read/Write Operation I I • Organization . . . I • Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector - Two 8K-Byte/4K-Word Parameter Sectors

P686

Contextual Info: TOSHIBA 1. TMP68652 INTRODUCTION The TM P68652 MPCC form ats, tran sm its, and receives synchronous se ria l d ata while supporting bit-oriented protocols BOP or byte-control protocols (BC P). The p a r a lle l b u s of the M PCC re a d ily in te r fa c e s w ith th e 6 8 0 0 an d T L C S -6 8 0 0 0

IMSG176/8

Contextual Info: TVP3027 VIDEO INTERFACE PALETTE XLAS106-MAY 1995 • Direct Interfacing to Video RAM • Supports Color Depths of 4-, 8-, 16-, 24-, and 32-Blt/Plxel • 64-Bit-Wide Pixel Bus • Supports Overscan For Creation of Custom Screen Borders • Color-Keyed Switching of Direct Color and

Contextual Info: SM/SMJ34061 VIDEO SYSTEM CONTROLLER JULY 1 98 7 • Generates User-Programmable Control Signals Horizontal Sync, Vertical Sync, and Blanking Which Support a Broad Range of Raster-Scan Display Systems with Varying Resolutions and Scan Rates S M J 3 4 0 6 1 G B . . . 68-P IN PGA

Contextual Info: TVP3026 VIDEO INTERFACE PALETTE X L A S 0 9 8 A - MAY 1995 | • Supports System Resolutions up to 1600 x 1280 at 76-Hz Refresh Rate • Versatile Pixel Bus Interface Supports Little- and Big-Endian Data Formats • Supports Color Depths of 4-, 8-, 16-, 24-,

Contextual Info: TOSHIBA TENTATIVE TMPN3120FE5M TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TMPN31 20FE5M Neuron Chip For Distributed Intelligent Control Networks L on W o r k s The Neuron Chip TMPN3120FE5M provides double the perform ance o f previous Neuron Chips. It supports a

Contextual Info: SN54ALVTH16721, SN74ALVTH16721 2.5-V/3.3-V 20-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCES139A - JULY 1998 - REVISED JANUARY 1999 SN54ALVTH16721 . . . W D PACKAGE SN74ALVTH16721 . . . DGG, DGV, OR DL PACKAGE TOP VIEW Support Mixed-Mode Signal Operation (5-V

CAD15-CAD8

Contextual Info: PCI1250A PC CARD CONTROLLER XCPS014 -D E C E M B E R 1997 * Peripheral Component Interconnect PCI Power Management Compliant • Supports Zoom Video With Internal Buffering • ACP11.0 Compliant • Programmable Output Select for CLKRUN • Packaged in 256-Pin BGA

Contextual Info: TL16PNP100A STANDALONE PLUG-AND-PLAY PnP CONTROLLER SLLS200B - MARCH 1995 - REVISED MARCH 1996 PnP Card Autoconfiguration Sequence Compliant Supports TVvo Logical Devices Decodes 10-Bit I/O Address Location With Programmable 1-, 2-, 4-, 8-, 16-Byte Block

SCAD002

Abstract: D3311 s3724
Contextual Info: SN74ALS6300 INPUT-SELECTABLE REFRESH TIMER D3311. DECEMBER 1989-REVISED JULY 1990 N PACKAGE Supports 16 Most Popular Microprocessor Speeds TOP VIEW C LK[ Supports Distributlve- and Hldden-Refresh Operations so[ 2 S1[ 3 S2 [ 4 S3 [ 5 Polarity Options Available for RFC,

high voltage linear regulator negative

Abstract: mag amp
Contextual Info: Power Supply Support Functions High Efficiency Linear Regulators UC1834/ UC2834/ UC3834 High Efficiency, Linear Regulator • Equally usable for either positive or negative regulators • 5A load with 0.5V Vin-Vout using external transistor • Internal precision positive and negative references

Contextual Info: SBP 9961 INTERRUPT CONTROLLER 1.0 INTRODUCTION 1.1 G E N E R A L D E SC R IP T IO N SBP 9961 T h e S B P 9961 C o n tro lle r is a ruggedized, m on olithic, program m able, m u ltifu n ction system support device fabricated w ith oxide separated Integrated In jection Lo gic l2 L technology. T h e S B P 9961 provides the S B P 9 9 0 0 series Fa m ily

Contextual Info: SN54LVT273, SN74LVT273 3.3-V ABT OCTAL D-TYPE FLIP-FLOPS WITH CLEAR I SCBS130E - MAY 1992 - REVISED JULY 1995 State-of-the-Art Advanced BICMOS Technology ABT Design for 3.3-V Operation and Low-Static Power Dissipation Support Mixed-Mode Signal Operation (5-V

Contextual Info: TSB41LV02 IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER SLLS355– MAY1999 D D D D D D D D D D D Fully Supports Provisions of IEEE 1394-1995 Standard for High-Performance Serial Bus† and the P1394a Supplement Fully Interoperable with FireWire and i.LINK Implementation of IEEE Std 1394

Contextual Info: SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS SLLS292A – APRIL 1998 – REVISED JANUARY 2000 D D D D D D D D D D DGG PACKAGE TOP VIEW 9 Channels for the Data and Control Paths of the Small Computer Systems Interface (SCSI) Supports Single-Ended and Low-Voltage

Contextual Info: SN75LVDM976, SN75LVDM977 9-CHANNEL DUAL-MODE TRANSCEIVERS SLLS292B – APRIL 1998 – REVISED JANUARY 2000 D D D D D D D D D D DGG PACKAGE TOP VIEW 9 Channels for the Data and Control Paths of the Small Computer Systems Interface (SCSI) Supports Single-Ended and Low-Voltage

Contextual Info: TFP401, TFP401A TI PanelBus DIGITAL RECEIVER SLDS120 - MARCH 2000 D D D D D D D Supports UXGA Resolution Output Pixel Rates Up to 165 MHz Digital Visual Interface (DVI) Specification Compliant1 True-Color, 24 Bit/Pixel, 16.7M Colors at 1 or 2-Pixels Per Clock

Contextual Info: SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT SCES295D – JUNE 2000 – REVISED DECEMBER 2000 D D D D DBV OR DCK PACKAGE TOP VIEW Supports 5-V VCC Operation Input and Open-Drain Output Accept Voltages up to 5.5 V Latch-Up Performance Exceeds 100 mA Per

rneg2

Contextual Info: QT1F-Plus Device Quad T1 Framer-Plus TXC-03103C DESCRIPTION • D4 SF, ESF including HDLC Link support , and transparent framing modes • Encodes/decodes AMI/B8ZS and forced ones density line codes • Fractional T1 gapped clock • Monitor function for frame pulse, clock and data

VTXP-6

Abstract: TXC-06951 g803 Motorola 0X69 TXC-06951-MB 98822
Contextual Info: VTXP-6 Device STM-1/STS-3 SDH/SONET TU/VT Processor and Cross Connect TXC-06951 DATA SHEET PRELIMINARY TXC-06951-MB, Ed. 5 March 2006 FEATURES APPLICATIONS • Supports two line ports using the standard byte wide 19.44 MHz Telecom Bus, or a single line port using the standard byte wide 77.76 MHz Telecom Bus.

Contextual Info: SN74LVC1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCES221D – APRIL 1999 – REVISED JANUARY 2001 D D D D DBV OR DCK PACKAGE TOP VIEW Supports 5-V VCC Operation Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per

BCT8373A

Contextual Info: SN54BCT8373A, SN74BCT8373A SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES SCBS044F – JUNE 1990 – REVISED JULY 1996 D D D D D description The ’BCT8373A scan test devices with octal D-type latches are members of the Texas Instruments SCOPE testability integratedcircuit family. This family of devices supports IEEE