SXT6282 Search Results

footprint plcc 208

Abstract: PLASTIC QUAD FLAT PACK 160 PINS DIMENSION LXT304A LXT305A LXT307 LXT310 LXT317 LXT318 LXT325 A 3120 8 Pins ICs
Contextual Info: Fall 1998 Communication ICs Data Book Table 1: Telecom Product/Packages Product Table 1: Telecom Product/Packages Product Package Package SXT6051 208 QFP SXT6251 208 QFP SXT6282 144-Pin LQFP LXT300Z/301Z 28-Pin DIP and 28-Pin PLCC LXT304A 28-Pin DIP and 28-Pin PLCC

Contextual Info: Product Overview JUNE 1998 SXT6282 Octal E1 Digital Interface with CRC-4 Monitoring and Jitter/ Wander Suppression General Description Features The SXT6282 is an independent eight-channel El digital interface. It integrates an E l dejitter phase locked loop, an

E1 HDB3

Abstract: SXT6234 LEVEL ONE COMMUNICATIONS G703 G704 LXT334 t j9h mux E1 E1 frame
Contextual Info: DATA SHEET SEPTEMBER, 1998 Revision 1.1 SXT6282 Octal E1 Digital Interface with CRC-4 Monitoring and Jitter/Wander Suppression General Description Features SXT6282 is an eight-channel E1 digital interface. It integrates an E1 dejitter phase locked loop, an E1 retiming

LXT902

Abstract: Evaluation Board SXT6234 t1.403 National Standard for Telecommunications PAIRGAIN campus multiplexing demultiplexing e2 e3 wireless lan 10 KM circuit LXT901A LXT904 LXT905 LXT906
Contextual Info:   Networking Networking Product Line Summary  Applications Part Number Features 10 Mbps Ethernet Transceivers Ethernet Interface Adapter Universal

LXT6234

Abstract: LXT6282 E1 HDB3
Contextual Info: Data Sheet MARCH 1999 Revision 2.0 LXT6282 Octal E1 Digital Interface with CRC-4 Monitoring and Jitter/Wander Suppression General Description Features LXT6282 is an eight-channel E1 digital interface. It integrates an E1 dejitter phase locked loop, an E1 retiming

Contextual Info: Data Sheet LXT6282 MARCH 1999 Revision 2.0 Octal E1 Digital Interface with CRC-4 Monitoring and Jitter/Wander Suppression General Description Features LXT6282 is an eight-channel E l digital interface. It inte­ grates an E l dejitter phase locked loop, an E l retiming

san francisco telecom

Abstract: X1HB 001H MTC21 SXT6251 MTC11 MTD16 P1396 MTC13 MTC15
Contextual Info: DATA SHEET MAY 1998 Revision 1.1 SXT6251 21 E1 SDH Mapper General Description Features The SXT6251 21E1 Mapper performs asynchronous mapping and demapping of 21 E1 PDH signals into SDH. The PDH side interfaces with E1 LIUs and framers via NRZ Clock & Data, while the SDH side uses a standard Telecom

G-783

Abstract: SDH -209 AN107 LXT380
Contextual Info: Timing Interface Using the LXT380 Application Note January 2001 Order Number: 249129-001 As of January 15, 2001, this document replaces the Level One document known as AN107. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual