SY100S891JCTR Search Results

Contextual Info: 'j•BIT R E G i S i E R F i SYNERGY T R A N S C E IVi-iR fliC O N D U C 7 Oh ■ 25 ohm cut-off bus outputs ■ 50 ohm receiver outputs ■ Transm it and receive registers with separate clocks ■ 1500ps max. delay from C L K i to Bus Outputs BUS ■ 1500ps max. delay from CLK 2 to Receiver Outputs

SY100S891

Abstract: SY100S891JC SY100S891JCTR
Contextual Info: Micrel, Inc. 5-BIT REGISTERED TRANSCEIVER FEATURES SY100S891 SY100S891 DESCRIPTION 25Ω cut-off bus outputs 50Ω receiver outputs Transmit and receive registers with separate clocks 1500ps max. delay from CLK1 to Bus Outputs BUS 1500ps max. delay from CLK2 to Receiver Outputs (Q)

Contextual Info: * 5-BIT REGISTERED TRANSCEIVER SYNERGY SY100S891 SEMICONDUCTOR DESCRIPTION FEATURES • 25 ohm cut-off bus outputs ■ 50 ohm receiver outputs ■ Transmit and receive registers with separate clocks ■ 1500ps max. delay from CLKi to Bus Outputs BUS ■ 1500ps max. delay from CLK2 to Receiver Outputs

Contextual Info: 5-BIT REGISTERED TRANSCEIVER FEATURES SY100S891 DESCRIPTION 25Ω cut-off bus outputs 50Ω receiver outputs Transmit and receive registers with separate clocks 1500ps max. delay from CLK1 to Bus Outputs BUS 1500ps max. delay from CLK2 to Receiver Outputs (Q)

Contextual Info: * 5-BIT REGISTE RED TR AN SCEIVER SYNERGY SEMICONDUCTOR FEATURES SY100S891 DESCRIPTION • 25 ohm cut-off bus outputs ■ 50 ohm receiver outputs ■ Transmit and receive registers with separate clocks ■ 1500ps max. delay from CLKi to Bus Outputs BUS ■ 1500ps max. delay from CLK2 to Receiver Outputs

PS 1025

Abstract: SY100S891 SY100S891JC SY100S891JCTR
Contextual Info: * 5-BIT REGISTERED TRAN SC EIVER SYNERGY SY100S891 S E M IC O N D U C T O R DESCRIPTION FEATURES 25 ohm cut-off bus outputs 50 ohm receiver outputs Transmit and receive registers with separate clocks 1500ps max. delay from CLK 1 to Bus Outputs BUS 1500ps max. delay from CLK2 to Receiver Outputs

SY100S891

Abstract: SY100S891JC SY100S891JCTR
Contextual Info: 5-BIT REGISTERED TRANSCEIVER FEATURES SY100S891 DESCRIPTION 25Ω cut-off bus outputs 50Ω receiver outputs Transmit and receive registers with separate clocks 1500ps max. delay from CLK1 to Bus Outputs BUS 1500ps max. delay from CLK2 to Receiver Outputs (Q)

PS 1025

Abstract: D 400 transistor SY100S891 SY100S891JC SY100S891JCTR
Contextual Info: 5-BIT REGISTERED TRANSCEIVER FEATURES SY100S891 FINAL DESCRIPTION 25Ω cut-off bus outputs 50Ω receiver outputs Transmit and receive registers with separate clocks 1500ps max. delay from CLK1 to Bus Outputs BUS 1500ps max. delay from CLK2 to Receiver Outputs (Q)