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    Untitled

    Abstract: No abstract text available
    Text: « 01/Iie n /« V LOW-POWER HEX PECL-TO-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FEATURES PRELIMINARY SY100S390 DESCRIPTION The SY100S390 is a hex PECL-to-TTL translator for converting 100K logic levels to TTL logic levels. Unlike other level translators, the SY100S390 operates using only one


    OCR Scan     		PDF 01/Iie SY100S390 SY100S390 28-pin T0Q13fil

    F100K

    Abstract: SY100S351
    Text: * SYNERGY H E X D F L IP ' F L 0 P SY100S351 S E M IC O N D U C T O R _ DESCRIPTION FEATURES Max. toggle frequency of 700MHz Clock to Q max. of 1200ps min. of -98m A ESD protection of 2000V Ie e Industry standard 100K ECL levels Extended supply voltage option:


    OCR Scan     		PDF SY100S351 700MHz 1200ps -98mA F100K SY100S351 D24-1 SY100S351FC F100K

    Untitled

    Abstract: No abstract text available
    Text: A SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE e V W C D / 'V sE ^ ooXd u c to r C lo c k w o rk s SY10H842 SY100H842 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew


    OCR Scan     		PDF SY10H842 SY100H842 300ps 500ps SY10/100H842 Z16-1 Y100H

    Untitled

    Abstract: No abstract text available
    Text: V SYNERGY ClockWorks PRELIMINARY in fo r m a tio n SY89421L HIGH PERFORMANCE PHASE LOCKED LOOP SEMICONDUCTOR FEATURES DESCRIPTION • 1.12GHz maximum VCO frequency ■ 30 to 560MHz reference input operating frequency ■ External 2.5GHz VCO capability ■ Low jitter differential design


    OCR Scan     		PDF SY89421L SY89421L 560MHz 2500MHz 1120MHz. SY89421ZC Z20-1 T0Q13

    Untitled

    Abstract: No abstract text available
    Text: * e v w 3 -B IT S C A N N A B L E R E G IS T E R E D B U S T R A N S C E IV E R 1" A N i i O t l V t H c o /'v SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES 1500ps max. clock to bus data transm it 1000ps max. clock to Q (data receive) Extended 100E V ee range of -4 .2 V to -5 .5 V


    OCR Scan     		PDF 1500ps 1000ps C10E/100E337 SY10E337JC J28-1 SY10E337JCTR SY100E337JC SY100E337JCTR

    Untitled

    Abstract: No abstract text available
    Text: * LOW POWER HEX TTL-to-ECL TRANSLATOR SYNERGY SY100S324 SEMICONDUCTOR FEATURES DESCRIPTION The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL compatible with differential outputs that can either be


    OCR Scan     		PDF SY100S324 SY100S324 SY100S324DC D24-1 SY100S324FC F24-1 100S324JC J28-1 SY100S324JCTR

    Untitled

    Abstract: No abstract text available
    Text: * SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • PECL version of popular ECLinPS E111 ■ Low skew ■ Guaranteed skew spec ■ V bb output ■ TTL enable input ■ Selectable TTL or PECL clock input ■ Single +5V supply


    OCR Scan     		PDF SY100S811 SY100S811JC J28-1 SY100S811JCTR SY100S811ZC Z16-1 SY100S811ZCTR

    DALE crystal 16Mhz

    Abstract: SY89429A SY89429AJC
    Text: * Clockworks PRELIMINARY SY89429A FREQUENCY SYNTHESIZER SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ 25 to 400MHz differential PECL outputs 10ps rms max. jitter Minimal frequency over-shoot Synthesized architecture Serial 3 wire interface


    OCR Scan     		PDF SY89429A 400MHz SY89429A 800MHz. S0Q13Ã SY89429AJC J28-1 SY89429A2C Z28-1 DALE crystal 16Mhz

    SY2BP

    Abstract: SY2BP00
    Text: *SYNERGY UNIVERSAL SYSTEM ELEMENT USE SEMICONDUCTOR FEATURES SY2BP00 DESCRIPTION Highest density logic via unique 6-transistor cell: + greatest functionality per unit area + shortest propagation delays 2,184 core cells yield up to 3,640 routeable (equivalent) gates or 242 0-type flip-flops


    OCR Scan     		PDF SY2BP00 SY2BP00 T0Q13A1 0D0Q514 SY2BP

    MBT- 100K

    Abstract: No abstract text available
    Text: SYNERGY SEMI CON D U CT OR *SYNERGY S7E ]> • T0013A1 0000033 SE2 I SY10484-3.5/4/5/6 4K x 4 ECL RAM SY100484-3.5/4/5/6 SY101484-3.5/4/5/6 SEMICONDUCTOR -T -H é -Z 3 '0 8 ■ FEATURES Address access tim e, tAA: 3.5/4/5/6ns max. Chip select access tim e, tAc: 3ns max.


    OCR Scan     		PDF T0013A1 500ps SY10484-3 SY100484-3 SY101484-3 SY10/100/101484 16384-bit 4096-words-by-4-bits 10K/100K SY100age MBT- 100K

    Untitled

    Abstract: No abstract text available
    Text: * 9-BIT HOLD REGISTER SYNERGY SY10E143 SY100E143 SEMICONDUCTOR DESCRIPTION FEATURES • 700MHz min. operating frequency ■ Extended 100E VEE range of -4.2V to -5.5V ■ 9 bits wide for byte-parity applications ■ Asynchronous Master Reset ■ Dual clocks


    OCR Scan     		PDF SY10E143 SY100E143 700MHz MC10E/100E143 SY10/100E143 SY10E143JC J28-1 SY10E143JCTR SY100E143JC

    Untitled

    Abstract: No abstract text available
    Text: * TRIPLE 4-INPUT MULTIPLEXER WITH ENABLE SYNERGY SY100S371 SEMICONDUCTOR FEATURES • ■ Max. propagation delay of 1000ps ■ Ie e DESCRIPTION The SY100S371 is an ultra-fast triple 4-input multiplexer with true and complementary outputs designed for use in


    OCR Scan     		PDF SY100S371 1000ps SY100S371 000225b D24-1 371FC F24-1 371JC J28-1

    Untitled

    Abstract: No abstract text available
    Text: ^ 4-BIT SERIAL/PARALLEL CONVERTER SYNERGY SY10E445 SY100E445 SEMICONDUCTOR FEATURES DESCRIPTION On-chip clock ^4 and -¡-8 E x te n d e d 1 0 0 E V e e r a n g e o f - 4 . 2 V to - 5 . 5 V 2.5Gb/s data rate capability Differential clock and serial inputs V b b o u t p u t fo r s in g le -e n d e d u s e


    OCR Scan     		PDF SY10E445 SY100E445 MC10E/100E445 10E445JC J28-1 10E445JCTR SY100E445JC 100E445JCTR

    SY100S811

    Abstract: SY100S811JC SY100S811JCTR SY100S811ZC SY100S811ZCTR
    Text: * SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL SYNERGY S E M IC O N D U C T O R FEATURES DESCRIPTION PECL version of popular ECLinPS E111 Low skew Guaranteed skew spec V bb output TTL enable input Selectable TTL or PECL clock input Single +5V supply Differential internal design


    OCR Scan     		PDF SY100S811 SY100S811 SY100S811JC J28-1 SY100S811JCTR SY100S811ZC Z16-1 SY100S811ZCTR

    100474

    Abstract: SY100474 SY101474 Y1047
    Text: * SYNERGY SY 10474-3/4/5/7 S Y 1 00474-3/4/5/7 S Y 101474-3/4/5/7 1K X 4 E C L R A M S E M IC O N D U C T O R FEA TU R E S D E S C R IP T IO N • Address access time, tAA: 3/4/5/7ns max. ■ Chip select access tim e, tAC: 2ns max. ■ Write pulse width, tww: 3ns min.


    OCR Scan     		PDF SY10474-3/4/5/7 SY100474-3/4/5/7 SY101474-3/4/5/7 500ps -300mA, -220mA 10K/100K SY10/100/101474-3FCF SY10/100/101474-3MCF F24-1 100474 SY100474 SY101474 Y1047

    SY100H841

    Abstract: SY10H841
    Text: SINGLE SUPPLY QUAD PECL-TO-TTL WITH OUTPUT ENABLE SYNERGY S E M IC O N D U C T O R FEATURES T he S Y 1 0 /1 0 0 H 8 4 1 a re s in g le s u p p ly , lo w ske w tran sla tin g 1:4 clo ck drivers. The devices fe a ture a 24m A TTL o utput stage, with AC perform ance specified into a 50pF load capacitance.


    OCR Scan     		PDF SY100H841 300ps 500ps SY10/100H841 DDDE313 SY10H841 SY100HB41 SY10H841ZC Z16-1 SY10H841ZCTR SY100H841 SY10H841

    Untitled

    Abstract: No abstract text available
    Text: * SO NET/S DH/ATM O C - 1 2 C L O C K R E C O V E R IN G T R A N S C E IV E R SYNERGY SEMICONDUCTOR FEATURES sy m ti2 DESCRIPTION • A complete SONET/SDH Transmitter & Receiver ■ Complies with Bellcore, CCITT and ANSI Specifications ■ Two on-chip PLLs: One for clock generation &


    OCR Scan     		PDF 44MHz 84MHz 100-pln SY69712 SY69712 R100-2)

    Untitled

    Abstract: No abstract text available
    Text: * 8-BIT RIPPLE COUNTER SYNERGY SY10E137 SY100E137 SEMICONDUCTOR FEATURES DESCRIPTION • 1.8GHz min. count frequency ■ Extended 100E V ee range of -4.2V to -5.5V ■ Synchronous and asynchronous enable pins ■ Differential clock input and data output pins


    OCR Scan     		PDF SY10E137 SY100E137 137JC J28-1 137JC

    Untitled

    Abstract: No abstract text available
    Text: * QUAD MULTIPLEXER/LATCH SYNERGY SY100S355 S E M IC O N D U C T O R FEATURES DESCRIPTION • Max. propagation delay of 110Ops ■ Max. enable to output delay of 1400ps ■ I e e min. of -80m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels


    OCR Scan     		PDF SY100S355 110Ops 1400ps F100K SY100S355 SY100S355DC D24-1 SY100S355FC F24-1

    SY100S321DC

    Abstract: D217 F100K SY100S321 2425U
    Text: * LOW-POWER 9-BIT INVERTER SYNERGY S E M IC O N D U C TO R FEATURES SY100S321 DESCRIPTION I M ax. p ro p a g a tio n d e la y o f 7 0 0 p s The SY100S321 is a monolithic 9-bit inverter. The device contains nine inverting buffer gates with single input and output.


    OCR Scan     		PDF SY100S321 700ps of-55mA F100K SY100S321 SY100S321DC D24-1 SY100S321FC F24-1 D217 F100K 2425U

    Mlt-3

    Abstract: No abstract text available
    Text: A F D D I/F A S T E T H E R N E T /A T M A D A P T IV E E Q U A L IZ IN G N E T W O R K T R A N S C E IV E R S Y M E B G Y S ^ tC ^ D U C T O R FEATURES PRELIMINARY INFORMATION SY67223A DESCRIPTION Compliant with ANSI X3T9.5 TP-PMD draft standard, IEEE 802.3 100BASE-TX Ethernet draft standard, and


    OCR Scan     		PDF SY67223A 100BASE-TX 155Mbps 28-pin PMID23 100BASE-TX) T0Q13 Mlt-3