T15E Search Results

AH-34

Abstract: Optimax FPF-34 4501LI 18E DBM SMTO-8 CAH-34 AH34
Contextual Info: TRIAX CORP/ OPTINAX INC lfiE » AH-34 • T15E724 GGQGM35 1 ■ _T-74-oq-o\ 100 to 2000 MHz TO-8 Cascadable Amplifier • High Gain: +16.0dB • Wideband: 100-2000MHZ • Power Output: +7,0dBm • Various Package Options see photo Surface Mounted (SMTO-8), Flatpack with flange (FPF),

Asus MONITOR MOTHERBOARD CIRCUIT MANUAL

Abstract: T2D 83 diode gp026 st GP025 82430TX 82371EB Asus PC MOTHERBOARD CIRCUIT schematic diode T75A Asus PC MOTHERBOARD CIRCUIT MANUAL 8272A floppy disk controller block diagram
Contextual Info: PRELIMINARY DRAFT Intel Extended Temperature 82371EB PCI-TO-ISA/IDE Xcelerator PIIX4E Datasheet  Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers  Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation Supported Kits for both Pentium and

82378ib

Contextual Info: A P M Ä M ! DM iP© I^[ìfflA'irD@ N] in te i 82378IB SYSTEM I/O SIO Provides the Bridge Between the PCI Bus and ISA Bus Arbitration for PCI Devices — Four PCI Masters are Supported — Fixed, Rotating, or a Combination of the Two 100% PCI and ISA Compatible

STLC5411

Abstract: DIP28 PLCC44 ST5421 ST5451 STLC5411FN STLC5411P
Contextual Info: STLC5411 2B1Q U INTERFACE DEVICE GENERAL FEATURES SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR BOTH ISDN AND PAIR GAIN APPLICATIONS MEETS OR EXCEEDS ANSI U.S. AND ETSI EUROPEAN STANDARD SINGLE 5V SUPPLY DIP28 AND PLCC44 PACKAGE HCMOS3A SGS-THOMSON ADVANCED

kjd1

Abstract: t17c marking T18C UT63M125 application notes 1553B F801 UT1553B T16B 3F6 smd smd 3F9
Contextual Info: UT1553B RTR Remote Terminal with RAM FEATURES ❐ Complete MIL-STD-1553B remote terminal interface ❐ 1K x 16 of on-chip static RAM for message data, completely accessible to host ❐ Self-test capability, including continuous loop-back ❐ ❐ ❐ ❐ MCSA 4:0

T3D 34 diode

Abstract: 82440LX Diode T3D 57 t57b T27b t59b T31C Transistor t59c ISA BUS spec t119
Contextual Info: E DATASHEET ADDENDUM 82371AB PIIX4 PCI ISA IDE Xcelerator Timing Specifications September 1997 Order Number: 290548-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions

Edd 44

Abstract: audio transformer GCI DIP28 PLCC44 ST5451 STLC5412 STLC5412FN STLC5412P STLC5464 STLC5465
Contextual Info: STLC5412 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE PRELIMINARY DATA GENERAL FEATURES SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS MEETS OR EXCEEDS ETSI EUROPEAN STANDARD SINGLE 5V SUPPLY DIP28 AND PLCC44 PACKAGE

P55i

Abstract: HY29F040A P12-I
Contextual Info: HY29F040A Series 512K x 8-bit CMOS 5.0 volt-only, Sector Erase Flash Memory KEY FEATURES • 5.0 V ± 10% Read, Program, and Erase - Minimizes system-level power requirements · High performance - 55 ns access time · Compatible with JEDEC-Standard Commands

Contextual Info: “H Y U N D A I HY29F040 Series 512K x 8-bit CMOS 5.0 volt-only, Sector Erase Flash Memory KEY FEATURES • 5.0 V ± 10% Read, Program, and Erase - Minimizes system-level power requirements • High performance - 120 ns access time • Compatible with JEDEC-Standard Commands

Contextual Info: * 1 SCS-THOMSON / R a n a @ i i L i g r e w n e § S T L C 5 4 1 1 2B1Q U INTERFACE DEVICE ADVANCE DATA G ENERAL FEATURES • SINGLE CHIP 2B1Q LINE CODE TRANS­ CEIVER ■ SUITABLE FOR BOTH ISDN AND PAIR GAIN

Edd 44

Abstract: DIP28 PLCC44 ST5451 STLC5412 STLC5412FN STLC5412P STLC5464 STLC5465 dect scrambler
Contextual Info: STLC5412 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE PRELIMINARY DATA GENERAL FEATURES SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS MEETS OR EXCEEDS ETSI EUROPEAN STANDARD SINGLE 5V SUPPLY DIP28 AND PLCC44 PACKAGE

HY29F200

Abstract: HY29F200B HY29F200T
Contextual Info: HY29F200T/B Series 2 Megabit 5.0 volt-only Sector Erase Flash Memory KEY FEATURES • 5.0 V ± 10% Read, Program, and Erase - Minimizes system-level power requirements · High performance - 70 ns access time · Compatible with JEDEC-Standard Commands - Uses software commands, pinouts, and

MIL-M-24519

Contextual Info: 7 TH IS DRAWING IS U N P U B LIS H E D . RELEASED FOR 6 5 4 2 3 PUBLICATION LOC ALL RIGHTS RESERVED. COPYRIGHT - D IS T 16 AJ By - C = t0.25 R E V IS IO N S LTR D E SC RIPTIO N Typ REVISED PER DATE DWN RK HMR 11 MAR 11 E C O -1 1 -0 0 5 0 3 0 APVD ° [+.01 o] ' TK

Contextual Info: HY29F040 Series 512K x 8-bit CMOS, 5.0 Volt-only, Sector Erase Flash Memory KEY FEATURES • 5.0 V ± 10% Read, Program, and Erase - Minimizes system-level power requirements • High performance - 90 ns access time • Low Power Consumption - 20 mA typical active read current

AI23

Abstract: MSM66591 5P10 1558 bcb 0P97 11P11 AD162 AD164 I0044 P120A
Contextual Info: ¡ MSM66591 ユーザーズマニュアル CMOS 16bit マイクロコントローラ 沖電気工業株式会社 '99•3作成 ご 注 意 1. 本書に記載された内容は製品改善及び技術改良等により将来予告なしに変更することがありま

tlc 5421

Abstract: ocs ctc tlc5411 723T HDC3
Contextual Info: n = J S G S -T H O M S O N S T L C 5411 2B1Q U INTERFACE DEVICE GENERAL FEATURES • SINGLE CHIP 2B1Q LINE CODE TRANS­ CEIVER . SUITABLE FOR BOTH ISDN AND PAIR GAIN APPLICATIONS ■ MEETS OR EXCEEDS ANSI U.S. AND ETSI EUROPEAN STANDARD . SINGLE 5V SUPPLY

T13G

Abstract: T18E t12j A6211 RTS-34 t18f 63M125 t17j UT176 RTS-28
Contextual Info: UTI760A RTS Remote Terminal for Stores FEATURES ❐ Complete MIL-STD-1760A Notice I through III ❐ ❐ ❐ ❐ ❐ ❐ ❐ remote terminal interface 1K x 16 of on-chip static RAM for message data, completely accessible to host Self-test capability, including continuous loop-back

Contextual Info: “H Y U N D A I HY29F080 Series 1M x 8-bit CMOS 5.0 volt-only, Sector Erase Flash Memory KEY FEATURES 5.0 V ± 10% Read, Program, and Erase - Minimizes system-level power requirements High performance - 55 ns access time Internal Programming Algorithms - Automatically programs and verifies data at a

Contextual Info: Y I I I I VI A I I U 11 U l l l HY29F200T/B Series 2 Megabit 5.0 volt-only Sector Erase Flash Memory KEY FEATURES • 5.0 V ± 10% Read, Program, and Erase - Minimizes system-level power requirements • High performance - 70 ns access time • Compatible with JEDEC-Standard Commands

dmo 365 r

Abstract: RF MODULE CIRCUIT DIAGRAM dect Edd 44 NT 101 DIP28 PLCC44 ST5451 STLC5412 STLC5412FN STLC5412P
Contextual Info: STLC5412 2B1Q U INTERFACE DEVICE ENHANCED W ITH DECT MODE PRELIMINARY DATA GENERAL FEATURES • SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER ■ SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS ■ MEETS OR EXCEEDS ETSI EUROPEAN STANDARD ■ SINGLE 5V SUPPLY . DIP28 AND PLCC44 PACKAGE

Contextual Info: / T T SGS-IHOMSON * l i . M g[]MI[LI(§Ij»[](§S STLC5412 2B1Q U INTERFACE DEVICE ENHANCED W ITH DECT M ODE PR ELIM IN A R Y DATA G EN ER AL FEATURES • SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER ■ SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS ■ MEETS OR EXCEEDS ETSI EUROPEAN

dmo 365 rn

Contextual Info: STLC5412 2B1Q U INTERFACE DEVICE ENHANCED W ITH DECT MODE PRELIMINARY DATA GENERAL FEATURES • SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER ■ SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS ■ MEETS OR EXCEEDS ETSI EUROPEAN STANDARD ■ SINGLE 5V SUPPLY ■ DIP28 AND PLCC44 PACKAGE

T3D 77

Abstract: T3D 34 diode T3D 46 diode Cirrus Logic Voyager Diode T3D 57 T3D 76 CL-PS7111 PCMCIA SRAM Card T3D 43 diode T3D 45 diode
Contextual Info: CL-PS6700 Preliminary Data Book FEATURES • Direct interface to CL-PS7111 low-power microcontroller — Custom multiplexed address/data bus for low pin count — Supports 13- and 18-MHz operating frequencies ■ Fully compatible with PC Card PCMCIA Release

Edd 44

Abstract: m51x DIP28 PLCC44 ST5451 STLC5412 STLC5412FN STLC5412P STLC5464 STLC5465
Contextual Info: STLC5412 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE PRELIMINARY DATA GENERAL FEATURES SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS MEETS OR EXCEEDS ETSI EUROPEAN STANDARD SINGLE 5V SUPPLY DIP28 AND PLCC44 PACKAGE