T28B Search Results

Dp 104

Abstract: BL-T28X-31 BL-T40B-31 PI-52 BL-T36A-31 BL-T36X-31
Contextual Info: [ j LED Component B et L ux TH R E E D IG IT D ISPLA Y BL-T2SA-31 is BL-T28X-31 Series DIG.1 DIG .2 DIE.3 A Q Q o 'E ^ U e . //c L k = L lo BL-T28B-31 « BL-T30X-31 Series BL-T30A-31 DIG.1 DIH.Z DIG.3 A D I f //g //B Jlo U loSS s D DP BL-T3QB-31 *045 BL-T36X-31 Series

7 SEGMENT DISPLAY COMMON CATHODE

Abstract: common anode 7-segment display 7 segment common cathode LED display
Contextual Info: Three Digits Seven Segment LED display Chip Common Cathode Common Anode BL-T25X-31 Series Material BL-T28X-32 Series BL-T25A-31 BL-T28A-32 BL-T25B-31 BL-T28B-32 BL-T28X-32 Series BL-T28C-32 BL-T28D-32 For more, please visit http://www.betlux.com Three Digits Seven Segment LED display

Asus MONITOR MOTHERBOARD CIRCUIT MANUAL

Abstract: T2D 83 diode gp026 st GP025 82430TX 82371EB Asus PC MOTHERBOARD CIRCUIT schematic diode T75A Asus PC MOTHERBOARD CIRCUIT MANUAL 8272A floppy disk controller block diagram
Contextual Info: PRELIMINARY DRAFT Intel Extended Temperature 82371EB PCI-TO-ISA/IDE Xcelerator PIIX4E Datasheet  Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers  Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation Supported Kits for both Pentium and

Contextual Info: A B W A N O B O N IP O R Q W O Q N in te i 82091AA ADVANCED INTEGRATED PERIPHERAL AIP • Single-Chip PC Compatible I/O Solution for Notebook and Desktop Platforms: — 82078 Floppy Disk Controller Core — Two 16550 Compatible UARTs — One Multi-Function Parallel Port

Contextual Info: intJ. 82375EB PCI-EISA Bridge PCEB Provides the Bridge Between the PCI Bus and EISA Bus 32-Bit Data Paths 100% PCI and EISA Compatible — PCI and EISA Master/Slave Interface — Directly Drives 10 PCI Loads and 8 EISA Slots — Supports PCI at 25 MHz to 33 MHz

T3D 34 diode

Abstract: 82440LX Diode T3D 57 t57b T27b t59b T31C Transistor t59c ISA BUS spec t119
Contextual Info: E DATASHEET ADDENDUM 82371AB PIIX4 PCI ISA IDE Xcelerator Timing Specifications September 1997 Order Number: 290548-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions

Contextual Info: Features • 2.7 to 3.6V Supply - Full Read and Write Operation • Low Power Dissipation - 8 mA Active Current - 50 nA CMOS Standby Current • Read Access Time - 250 ns • Byte Write - 3 ms • Direct Microprocessor Control - DATA Polling - READ/BUSY Open Drain Output on TSOP

5757H

Abstract: A1318 U DP83905
Contextual Info: S e m i c o n d u c t o r DP83905 AT/LANTIC AT Local Area Network Twisted-Pair Interface Controller General Description Features The AT/LANTIC AT Local Area Network Twisted-pair Inter­ face Controller is a CMOS VLSI device designed for easy implementation of CSMA/CD local area networks.

300GP

Abstract: Socket AM2 MII Processor
Contextual Info: Cyrix M II" DATA BOOK February 26, 1999 Updates for this manual can be obtained from Cyrix Web site: www.cyrLx.com. 1998 Copyright Cyrix Corporation. All rights reserved. Hinted in the United States of America Hademark Acknowledgments: Cyrix is a registered trademark of Cyrix Corporation.

386SX

Abstract: 82385SX t23b 82358 82385 t44a 387SX SA9C a82385 intel 386 SX LP
Contextual Info: in te i 82385SX HIGH PERFORMANCE CACHE CONTROLLER Im proves 386 SX System Perform ance — Reduces A verage CPU W ait States to Nearly Zero — Zero W ait State Read Hit — Zero W ait State Posted Mem ory W rites — Allows O ther Masters to Access the

T55B

Abstract: T71A t19c t17c t61b t58b t57b T27b t65a T3D 62
Contextual Info: 82371AB PCI ISA IDE Xcelerator PIIX4 23.0 Clock, Reset, ISA Bus, X-Bus, and Host Timing Diagrams Figure 41. Clock Timing Period High Time PCICLK, SYSCLK, OSC 2.0V 0.8V Low Time Fall Time Rise Time Figure 42. Reset Inactive Timing SUS_STAT[1:2]# t2f PCIRST#, RSTDRV

t2g memory

Abstract: 140U -i6
Contextual Info: AMDÌ1 PRELIMINARY Élan SC300 Highly Integrateci, Low -Power, 32-B it M icrocontroller DISTINCTIVE CHARACTERISTICS • Highly integrated, single-chip CPU and system logic - Optimized for embedded PC applications - Combines 32 bit, x86 compatible, low-voltage

T23B

Abstract: figure t23b AB34 AN35 t19b T31B
Contextual Info: MII PROCESSOR Enhanced High Performance CPU  Advancing the Standards Electrical Specifications 4.0 ELECTRICAL SPECIFICATIONS 4.1 Electrical Connections This section provides information on electrical connections, absolute maximum ratings, recommended operating conditions, DC characteristics, and AC characteristics. All voltage

Contextual Info: AMDÌ1 PRELIMINARY Élan SC300 Highly Integrated, Low-Power, 32-Bit Microcontroller DISTINCTIVE CHARACTERISTICS - Zero wait-state access with 70 ns, Page mode DRAMs • Highly integrated, single-chip CPU and system logic - Supports up to 16 Mbyte system memory

0DC00H

Abstract: 27cxxx programming dwa 108 a lg LED monitor circuit diagram TRANSFORMER bck 02 007 valor fl1012 5757H PT4160 dwa 108 a pin diagram MAR7
Contextual Info: PRELIMINARY septemberi994 DP83907 AT/LANTIC » General Description Features The DP83907 Twisted-Pair Enhanced Coaxial Network In­ terface Controller is a CMOS VLSI device designed for easy implementation of CSMA/CD local area networks. Unique to the DP83907 is the integration of the entire bus

ewm d35

Abstract: 300gp cyrix 8086 opcode of mov ax,bx AK 0610 ami bios al29 az5 capacitor Cyrix 6x86 MX CPU Socket AM2 AK 061
Contextual Info: Cyrix M II" DÄIÄ BOOK February 22, 1999 Updates for this manual can be obtained from Cyrix Web site: www.cyrix.com. 1998 Copyright Cyrix Corporation. All rights reserved. Printed in the United States o f America Trademark Acknowledgments: Cyrix is a registered tradem ark o f Cyrix Corporation.

GP360

Abstract: RPX 200 GP425 T28b 2d graphics line drawing filling texture mapping CQ T4A X1Y11
Contextual Info: r CIRRUS LOGIC G r aph i cs Primitives: • Trapezoid fill for high speed graphics • Line drawing B it BLT Engine: • Three operand BitBLT source, pattern, and destination • Automatic pattern (texture) replication Page M e mo r y Interface: • XY to linear page memory address calculation

10BASE2

Abstract: 10BASE5 DP8390 DP83901 DP83905 NE2000 TPI20 LA17-23
Contextual Info: November 1995 DP83905 AT LANTIC TM AT Local Area Network Twisted-Pair Interface Controller General Description Features The AT LANTIC AT Local Area Network Twisted-pair Interface Controller is a CMOS VLSI device designed for easy implementation of CSMA CD local area networks

SC310-33

Contextual Info: AMDÌ1 PRELIMINARY Élan SC310 Single-Chip, 32-Bit, PC/AT Microcontroller DISTINCTIVE CHARACTERISTICS • Highly integrated, single-chip CPU and system logic - Optimized for embedded PC applications - Combines 32 bit, x86 compatible, low-voltage CPU with memory controller, PC/AT peripheral

mar750

Contextual Info: DP83905 DP83905 AT/LANTIC TM AT Local Area Network Twisted-Pair Interface Controller Literature Number: SNLS087A November 1995 DP83905 AT LANTIC TM AT Local Area Network Twisted-Pair Interface Controller General Description Features The AT LANTIC AT Local Area Network Twisted-pair Interface Controller is a CMOS VLSI device designed for easy

ISA S20

Abstract: DP83905 AT-LANTIC ISA S20 temperature transmitter MRD 532 DP83901 "Attachment Unit Interface" lsi aui isolation transformer AUI lsi MAR7 valor fl1012
Contextual Info: November 1995 DP83905 AT LANTIC TM AT Local Area Network Twisted-Pair Interface Controller General Description Features The AT LANTIC AT Local Area Network Twisted-pair Interface Controller is a CMOS VLSI device designed for easy implementation of CSMA CD local area networks

82358

Abstract: XC96 8251 intel microcontroller architecture F245B intel 82358 INTERFACING OF 8272 WITH 8086 EISA chip set 82355 ta 8271 hq intel 82355
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed fo r use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 M b ytes/S ec Maximum Data

ALL-07 PROGRAMMER

Abstract: sprint plus 48 ST62t30 gang programmer schematic ALL07 UNIVERSAL PROGRAMMER AND TESTER PAC DIP 40 RS232 STAG 200 interface ibm t30 laptop schematic diagram leaper-10 CABLE LEAPER-10 driver ibm t40 lcd needham family emp30
Contextual Info: 8-BIT MCUs DEVELOPMENT TOOLS DIRECTORY 1rst EDITION October 1997 1 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED. SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHO UT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

Cyrix M2 CPU

Abstract: Socket AM2 CYRIX CORPORATION Cyrix 6x86
Contextual Info: r Cyrix M II TM M obile CPU P re lim in a ry Data Sheet January 5, 1999 3:38 Addendums and other updates for this manual can be obtained from Cyrix Web site: www.cyrix.com Cyrix M M M OBI LE PROCESSOR IMianœdHghPerfonmnce CPU A N ational Semiconductor Company