T49B Search Results

82378ib

Contextual Info: A P M Ä M ! DM iP© I^[ìfflA'irD@ N] in te i 82378IB SYSTEM I/O SIO Provides the Bridge Between the PCI Bus and ISA Bus Arbitration for PCI Devices — Four PCI Masters are Supported — Fixed, Rotating, or a Combination of the Two 100% PCI and ISA Compatible

Contextual Info: Features Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Fast Read Access Time - 55 ns Internal Program Control and Timer 8K Bytes Boot Block With Lockout Fast Erase Cycle Time - 10 seconds Byte-by-byte Programming - 30 ns/Byte typical

78XXX

Abstract: AT49B AT12T T49B
Contextual Info: Features * * * * * * * * * * 2.7V to 3.6V Read/Write Operation Fast Read Access Time -120 ns Internal Erase/Program Control Sector Architecture - One 8K Words 16K bytes Boot Block with Programming Lockout - Two 4K Words (8K bytes) Parameter Blocks - One 496K Words (992K bytes) Main Memory Array Block

sony rxd7

Contextual Info: S O N Y C XD1700 E thernet S w itch Features: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Fully Integrated Ethernet Switch On A Chip Twenty Four 10Base-X Ports, Two 10/100Base-X Ports All Ports can be either Full or Half Duplex Low Per-Port Cost

48C1

Abstract: AT49BV008A AT49BV8192A 04XXX AT49BV8192AT-12RI
Contextual Info: Features • • • • • • • • • • 2.7V to 3.6V Read/Write Operation Fast Read Access Time - 90 ns Internal Erase/Program Control Sector Architecture - One 8K Words 16K Bytes Boot Block with Programming Lockout - Two 4K Words (8K Bytes) Parameter Blocks

t43b

Abstract: T78A t78b T49B T61-T62 T71-T72
Contextual Info: 82357 11.0 A.C. SPECIFICATIONS The A.C. specifications given in the following tables consist of output delays and input setup and hold requirements. The A.C. diagram’s purpose is to illus­ trate the clock edges and specific signal edges from which the timing parameters are measured. The

dma controller chip

Contextual Info: in tj, 82374EB EISA SYSTEM COMPONENT ESC • Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Wait State Cycles — Supports Byte Assembly/ Disassembly for 8-, 16- and 32-Bit

intel 82350

Abstract: intel 82352 82351 eisa intel 82357 intel 82358 82359 82350DT EISA Chip Set Design Guide 2LF 1418 82350DT
Contextual Info: in te i 82358DT EISA Bus Controller • Supports 82350 and 82350DT Chip Set Based Systems — Mode Selectable for Either 82350 or 82350DT Based Systems — Mode Defaults to 82350 Based Systems ■ Socket Compatible with the 82358 EISA Bus Controller ■ Provides EISA/ISA Bus Cycle

Contextual Info: Features • 2.7V to 3.3V Read/Write • Access Time - 90 ns * Sector Erase Architecture - Thirty 32K Word 64K Byte Sectors with Individual Write Lockout - Eight 4K Word (8K Byte) Sectors with Individual Write Lockout - Two 16K Word (32K Byte) Sectors with Individual Write Lockout

AT49BV/LV040

Contextual Info: Features * * * * * * * * * Single Voltage for Read and Write: 2.7V to 3.6V BV , 3.0V to 3.6V (LV) Fast Read Access Time -120 ns Internal Program Control and Timer 16K Bytes Boot Block With Lockout Fast Chip Erase Cycle Time -1 0 seconds Byte-by-Byte Programming - 30 ps/Byte Typical

Contextual Info: FILE 01 10\DT-49 01.6O~1.7O P.C.B. LAYOUT EEF NOTES: 1. Rating: 30 0 V 25A PITCH: 9.50m m 2. Insulation W ithstands Voltage: AC 2 0 0 0 V at 1 m im ute 3. Insulation Resistance: 500M H or m ore at DC500V 4. Using Tem perature Range: -40'C ~ + 105'C 5. Screw Torque Value: 14 kgf—cm

AT49LV040-12JC

Abstract: AT-49 AT49BV040 AT49BV040T AT49LV040 AT49LV040T at49 at49lv04012ti TSOP8 AT49 FLASH MEMORY FILE
Contextual Info: Features Single Voltage for Read and W rite: 2.7V to 3.6V BV , 3.0V to 3.6V (LV) Fast Read Access Tim e -1 2 0 ns Internal Program Control and Tim er 16K Bytes Boot Block With Lockout Fast Chip Erase Cycle Tim e -1 0 seconds Byte-by-Byte Programming - 30 ns/Byte Typical

82358

Abstract: 82357 intel 82358 82358DT t430 transistor TIMER ST3 82C594 intel 82357 v273 82C37
Contextual Info: in te i 82357 INTEGRATED SYSTEM PERIPHERAL ISP Provides Enhanced DMA Functions — IS A /E IS A DMA Compatible Cycles — All Transfers are Fly-By Transfers — 32-Bit Addressability — Seven Independently Programmable Channels — Provides Timing Control fo r 8-, 16-,

Contextual Info: Features Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Fast Read Access Time - 55 ns Internal Program Control and Timer 8K bytes Boot Block With Lockout Fast Erase Cycle Time -1 0 seconds Byte By Byte Programming - 30 |is/Byte typical

T100A video

Abstract: diode T74A t47a T42A ENA0217 LA71076SM T66A T89A t47b "AGC Amplifier"
Contextual Info: Ordering number : ENA0217 Monolithic Linear IC LA71076SM For VHS VTR Video Signal Processor Y/C/A single-chip Overview The LA71076SM is a video signal processing system IC that handles VHS VCR format. In addition to conventional video signal processing circuits, it integrates normal audio processing and record/playback FM-EQ circuits on a chip. The

82353

Abstract: intel 82358 82359 82353 intel intel 82353 82358DT
Contextual Info: 82353 ADVANCED DATA PATH • Dual Port Architecture Allows Host to Access Memory without Incurring EISA Arbitration ■ Provides Optimal i486 Burst Performance ■ High Performance, Flexible Memory Support: — Designed as a 16-Bit Slice which Interfaces 16, 32, or 64-Bit Memory

82374EB/82374SB

Contextual Info: Ä I W Ä 1 OMIF ISBM!rD@M in tei 82374EB EISA SYSTEM COMPONENT ESC Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Wait State Cycles — Supports Byte Assembly/

Contextual Info: intJ. 82374EB EISA SYSTEM COMPONENT ESC • Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Walt State Cycles — Supports Byte Assembly/ Disassembly for 8-, 16- and 32-Bit

T100A

Contextual Info: Ordering number : ENA0217 Monolithic Linear IC LA71076SM For VHS VTR Video Signal Processor Y/C/A single-chip Overview The LA71076SM is a video signal processing system IC that handles VHS VCR format. In addition to conventional video signal processing circuits, it integrates normal audio processing and record/playback FM-EQ circuits on a chip. The

Contextual Info: Features * 2.7V to 3.3V Read/Write * Access Time - 90 ns * Sector Erase Architecture - Thirty 32K Word 64K Byte Sectors with Individual Write Lockout - Eight 4K Word (8K Byte) Sectors with Individual Write Lockout - Two 16K Word (32K Byte) Sectors with Individual Write Lockout

1690H

Abstract: 79XXX 4096A 3DXXX
Contextual Info: Features * * * * * * * * * * 2.7V to 3.6V Read/Write Operation Fast Read Access Time -120 ns Internal Erase/Program Control Sector Architecture - One 8K Words 16K bytes Boot Block with Programming Lockout - Two 4K Words (8K bytes) Parameter Blocks - One 240K Words (480K bytes) Main Memory Array Block

T100A video

Abstract: t74a T49B t76a T89A gft47 T42A T66A t100a t3112
Contextual Info: 注文コード No. N A 0 2 1 7 LA71076SM モノリシックリニア集積回路 VHS 方式 VTR 用 映像･音声信号処 Y/C/A 1chip 概要 LA71076SM はVHS 方式の VTR 用信号処理 IC である。従来のビデオ信号処理に加え、ノーマル音声

T100A video

Abstract: diode T74A T42A pulse height analyzer ENA0217 LA71076SM t74a T66A T89A
Contextual Info: Ordering number : ENA0217 Monolithic Linear IC LA71076SM For VHS VTR Video Signal Processor Y/C/A single-chip Overview The LA71076SM is a video signal processing system IC that handles VHS VCR format. In addition to conventional video signal processing circuits, it integrates normal audio processing and record/playback FM-EQ circuits on a chip. The

82358

Abstract: T27b T48D T39a M82358 T49B T36D T19e
Contextual Info: 82358 6.0 A.C. SPECIFICATIONS A.C. Specifications for the EISA Bus Controller EBC TcaSE = 0°C to + 70°C, VCC = 5V ± 5 % , T ambient = 0°C to + 5 5 ”C Symbol Parameter 25 MHz Min 33 MHz Max Min Units Notes Max Host Interface Signals t1 t ia t ib 11c