TFBGA176 Search Results

Contextual Info: Package outline TFBGA176: plastic thin fine-pitch ball grid array package; 176 balls; body 6 x 15 x 0.7 mm B D SOT932-1 A ball A1 index area E A2 A A1 detail X e1 1/2 e e C ∅v ∅w b AB AA Y W V U T R P N M L K J H G F E D C B A M y y1 C C A B C M e e2 1/2 e

Contextual Info: JEITA Package Code P-TFBGA176-8x8-0.50 RENESAS Code PTBG0176KA-A Previous Code TBP-176BV MASS[Typ.] 0.11g D w S B E w S A x4 v y1 S y A1 A S S e A Z D Reference Symbol e R P N Dimension in Millimeters Min Nom D 8.0 E 8.0 Max v 0.15 w 0.20 J A 1.2 H A1 M L

TTBG0176GA-A

Contextual Info: JEITA Package Code T-TFBGA176-13x13-0.80 RENESAS Code TTBG0176GA-A Previous Code TBP-176A/TBP-176AV MASS[Typ.] 0.33g D w S B E w S A x4 v y1 S y A1 A S S ZD e A e R P N M Reference Symbol L B K Dimension in Millimeters Min Nom D 13.00 H E 13.00 G v J F Max

SSTUA32864

Abstract: SSTUA32866
Contextual Info: SSTUG32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01 — 23 April 2007 Product data sheet 1. General description The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

DDR2-800

Abstract: SSTUA32864 SSTUA32866 E6G3
Contextual Info: SSTUM32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 2 March 2007 Product data sheet 1. General description The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

STM32F429N

Abstract: STM32F429Ni
Contextual Info: STM32F427xx STM32F429xx ARM Cortex-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT Datasheet - production data Features &"'! • Core: ARM 32-bit Cortex®-M4 CPU with FPU,

Contextual Info: STM32F437xx STM32F439xx ARM Cortex-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera&LCD-TFT Datasheet - production data Features &"'! • Core: ARM 32-bit Cortex®-M4 CPU with FPU,

Contextual Info: SSTUB32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 04 — 22 April 2010 Product data sheet 1. General description The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

DDR2 SSTL class

Abstract: SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 DDR200 hp SSTU32866
Contextual Info: Memory interfaces Support logic for memory modules and other memory subsystems Portfolio overview PC100 to PC133 • AVC, ALVC, AVCM, and ALVCH series registered drivers • PCK2509 and PCK2510 series PLL clock buffers DDR200 to DDR266 • SSTV and SSTL series registered drivers

Q22x

Abstract: Q5A H7
Contextual Info: SSTUM32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 01 — 12 September 2006 Product data sheet 1. General description The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

SMD capacitor aa4 aa5

Abstract: J2 Q24A B sot932 Q5A H7 TFBGA176
Contextual Info: SSTUB32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 12 September 2006 Product data sheet 1. General description The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

AA7 smd diode

Abstract: J2 Q24A B Q22x data sheet for all smd components diode smd m7 DDR2-800 SSTUA32864 SSTUA32866 Q20x SMD capacitor aa4 aa5
Contextual Info: SSTUB32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 04 — 22 April 2010 Product data sheet 1. General description The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

silego

Abstract: Silego Technology DDR2-800 buffer marking code D22 q28b SILEGO q27b Q24A Q17B
Contextual Info: SLGSSTUB32868 DDR2 Configurable Registered Buffer With Parity Applications: • DDR2-800 memory modules • 28-bit, 1:2 registered buffer with parity • 1.8V data registers Features: • Supports High Density DDR2 Modules • Standard, High and Low Drive Versions

Contextual Info: SSTUM32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 2 March 2007 Product data sheet 1. General description The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

DDR2-800

Abstract: SSTUA32864 SSTUA32866 D12-D17
Contextual Info: SSTUB32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 03 — 7 March 2007 Product data sheet 1. General description The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

qualcomm msm 8255

Abstract: lm089hb1t04 GW 5819 DIODE IR3E11M1 IRM053U7 BS2F7VZ0165 lr36b11 LQ065T9DZ03 SHARP LM089HB1T04 LM081
Contextual Info: ✲_❄on❏❆n❏•.❇m ✷❂❈❆ ✣ ✳❍❊❅❂❖, J❑l❖ ✥✣, ✥✣✣✪ ✦:✤✬ ✷M CONTENTS Advanced Measures for Environmental Conservation as Management Policy. PACKAGES

ML86V8101

Abstract: ML610Q794G ML7147 ML610Q488 ML98 ML7138 ML7247-001
Contextual Info: Notes 1 The information contained in this document is provided as of october,2013. 2) The information contained herein is subject to change without notice. Before you use our Products, please contact our sales representative as listed below) and verify the

SENSOR MARKING CODEBOOK

Contextual Info: STM32F756xx ARM -based Cortex®-M7 32b MCU+FPU, 428DMIPS, up to 1MB Flash/320+16+ 4KB RAM, crypto, USB OTG HS/FS, ethernet, 18 TIMs, 3 ADCs, 25 com itf, cam & LCD Data brief Features • • • • • • • • • • • &"'! Core: ARM® 32-bit Cortex®-M7 CPU with FPU,