TFRA28J13 Search Results

TFRA28J133BAL-1

Abstract: AF8 "cross reference"
Contextual Info: Hardware Design Guide October 24, 2003 TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0 1 Introduction The documentation package for the TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0 system chip consists of the following documents: • The Supermapper Family Register Description and the Supermapper Family System Design Guide. These two documents are available on a password-protected website.

Contextual Info: Product Brief December 2001 TFRA28J13 Super Framer x28/x21 T1/E1/J1 x1 DS3 Features • Sources may be broadcast, looped back, or routed to/from a test-pattern generator or monitor. ■ Any DS1 or E1 channel may be routed through the jitter attenuator. ■

JJ20-11

Abstract: CEPT-E1 PRBS23 TFRA28J13 TS16 PRBS20 SLC-96 PBIT
Contextual Info: Product Description October 22, 2003 TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0 1 Introduction The documentation package for the TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0 system chip consists of the following documents: • ■ The Supermapper Family Register Description and the Supermapper Family System Design Guide. These documents

stm cl-30

Abstract: THSC2 LT 7659 psb 500-1.0 highway speed checker data sheet transistor 9012 SDH 209 ses 554 transistor fcs 9012 70010 FB
Contextual Info: Data Sheet March 2002 TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 1 Features • ■ ■ Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3, DS2, T1/E1/J1, and DS0/ E0/J0 applications. Implementation supports both linear 1 + 1, unprotected and ring (UPSR) network topologies.

0x80060

Abstract: 0x10061
Contextual Info: Supermapper Family Register Description, Revision 3 July 7, 2006 TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0 1 Register Description Overview 1.1 Introduction The Supermapper Family Register Description describes software register information for the following mapper system

LT 7659

Abstract: w20338 comcode 105 736 490 JT-G706 TMXF28155 TR-62411 GR-253-CORE JT-G704 1 into 12 demultiplexer circuit diagram 80212 502
Contextual Info: Data Sheet June 2002 TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 1 Features • ■ Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3, DS2, T1/E1/J1, and DS0/ E0/J0 applications. Implementation supports both linear 1 + 1, unprotected and ring (UPSR) network topologies.

Contextual Info: System Design Guide October 22, 2003 Supermapper Family System Design Guide 1 Introduction The Supermapper Family System Design Guide is divided into three sections. The first section lists the main differences between the various devices within the Supermapper family. This section is geared towards those customers unfamiliar

Contextual Info: Data Sheet March 2002 TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 1 Features • ■ ■ Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3, DS2, T1/E1/J1, and DS0/ E0/J0 applications. Implementation supports both linear 1 + 1, unprotected and ring (UPSR) network topologies.

Contextual Info: Supermapper Family Register Description, Rev 1 July 19, 2004 TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0 1 Register Description Overview 1.1 Introduction The Supermapper Family Register Description describes software register information for the following mapper system

RSY-5

Abstract: speex Vt-158 single slot
Contextual Info: Supermapper Family Register Description October 14, 2003 TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0 1 Register Description Overview 1.1 Introduction The Supermapper Family Register Description describes software register information for the following mapper system