TMS 3613 Search Results

raychem manual

Abstract: marking code software EAN-13 DUN14 raychem marking code TMS-WINTOTAL-SWARE
Contextual Info: RINTERCONNECT A DIVISION OF !@#$ ELECTRONICS WinTotal Wire marking software • Powerful wire marker design and print software • Familiar Windows user environment • Pre-loaded with Raychem Interconnect identification products • Powerful import and export functions:

Contextual Info: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency (NoBL) architecture eliminates dead cycles

Contextual Info: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency (NoBL) architecture eliminates dead cycles

Contextual Info: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency (NoBL) architecture eliminates dead cycles

Contextual Info: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency (NoBL) architecture eliminates dead cycles

Contextual Info: CY7C1371D CY7C1373D 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Functional Description Features • No Bus Latency (NoBL) architecture eliminates dead cycles

Contextual Info: CY7C1366C, CY7C1367C 9-Mbit 256 K x 36/512 K × 18 Pipelined DCD Sync SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined DCD Sync SRAM Features Functional Description  Supports bus operation up to 166 MHz  Available speed grade is 166 MHz  Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1366C, CY7C1367C 9-Mbit 256 K x 36/512 K × 18 Pipelined DCD Sync SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 166 MHz ■ Available speed grade is 166 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1366C, CY7C1367C 9-Mbit 256 K x 36/512 K × 18 Pipelined DCD Sync SRAM 9-Mbit (256 K × 36/512 K × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 166 MHz ■ Available speed grade is 166 MHz ■ Registered inputs and outputs for pipelined operation

MIL-C-17

Abstract: RG-211 MIL-W-85 M17/194-00001 M17 RG 180
Contextual Info: INTRODUCTION Times Microwave Systems designs and manufactures high performance coaxial cables, connectors and cable assemblies for a broad range of RF transmission applications. For more than 50 years, Times has been the leader in the development of new cable

y336

Abstract: Y164 Y165 Y143 88 TR 337 Y162 ST8601 Y163 TMS 3834 Transistor 337
Contextual Info: ST Sitronix ST8616 168 Segment Driver for STN LCD with Low-Voltage Drive PRELIMINARY Notice: This is not a final specification. Some parameters are subject to change 1 Features „ 168/160 output mode „ 4/8 bits data bus „ LCD drive voltage: 2.6 to 5.5 V

tms 3614

Abstract: 755-335 ST8600 ST 6244 A 06 / CT X112 ST8624 ST8632 x9301 X8302
Contextual Info: ST Sitronix ST8600 240 Channel Common Driver for STN LCD with High-Voltage Drive PRELIMINARY Notice: This is not a final specification. Some parameters are subject to change 1 Features „ Duty cycle up to 1/240 „ Intermediate voltage I/F „ LCD drive voltage: 43V max

TXC07900AIBG

Abstract: TXC-07900AIBG TSOP transmitter B020H OED155TM TXC-07900-MB VTXP-6 AU-AIS dk12b EK117
Contextual Info: OED155 Device Dual STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07900 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED155, is a dual STM-1 SDH framer and overhead terminator, virtual tributary

RX1d

Abstract: 3A184
Contextual Info: AsTriX Device CellBus Expansion Switch TXC-05840 DATA SHEET The AsTriX™ TXC-05840 CellBus Expansion Switch is a single chip switching solution for ATM systems. In order to meet the accelerating need for bandwidth in access systems, the AsTriX is designed to allow higher

TXC-07905-MB

Abstract: TXC-07905 OED622 B016H BP85H MSP SNCP h-12-H cu3ah B007H
Contextual Info: OED622 Device Dual STM-4/STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07905 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED622, is a dual STM-4/STM-1 SDH framer and overhead terminator, virtual

POS-PHY ATM format

Contextual Info: Sertopia Device UTOPIA Serializer TXC-05860 DESCRIPTION • In-band UTOPIA and POS-PHY Level 2 operating modes for cell and packet traffic • UTOPIA Level 2, and POS-PHY operating modes for cell and packet traffic • One UTOPIA port up to 800 Mbit/s

Contextual Info: ASPEN-PX Device ASPEN Port Expander TXC-05811 DATA SHEET FEATURES DESCRIPTION  The ASPEN-PX TXC-05811 , ASPEN Port Expander is a single chip solution for increasing the UTOPIA port density of ASPEN based systems. The ASPEN-PX device acts as a port expander enabling the ASPEN

Line Driver SHDSL

Abstract: lan SHDSL TXC-05806 TXC-06212 DP43 metd15 DP39 AETA
Contextual Info: ASPEN-PX Device ASPEN Port Expander TXC-05811 DATA SHEET DESCRIPTION FEATURES  • Interoperable with ASPEN TXC-05810B UTOPIA Level 2 interface • Provides port expansion for up to 64 UTOPIA Level 2 ports • Utilizes ASPEN ATM AccessEDGE firmware for

hp-1100

Abstract: TL3M hp1100 TXC-03453B
Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453B DATA SHEET SDH/SONET SIDE TELECOM BUS O-Bit Interfaces • Add/drop multiplexers • Digital cross connect systems • Broadband switching systems • Transmission equipment External Alarm Interfaces Drop Bus

Contextual Info: PHAST -12N Device STM-4/OC-12 SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06312 DESCRIPTION • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and clock synthesis - single 622.08 Mbit/s STM-4/OC-12 signal or - four 155.52 Mbit/s STM-1/OC-3 signals

intel 7882

Abstract: TXC-03453AI df2a df2e TXC-03453B
Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453B DATA SHEET SDH/SONET SIDE TELECOM BUS O-Bit Interfaces • Add/drop multiplexers • Digital cross connect systems • Broadband switching systems • Transmission equipment External Alarm Interfaces Drop Bus

HDB3

Abstract: df2a SOT
Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453B DATA SHEET Each of the three channels of the TL3M can map a DS3 line signal into an STM-1 TUG-3 or STS-3 STS-1 SPE SDH/SONET signal. An E3 signal can be mapped only into an STM-1 TUG-3. The TL3M interfaces to an STM-1 or STS-3 SDH/SONET signal

df2e

Abstract: TXC-03453 TXC-06103
Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453 DATA SHEET Each of the three channels of the TL3M can map a DS3 line signal into an STM-1 TUG-3 or STS-3 STS-1 SPE SDH/SONET signal. An E3 signal can be mapped only into an STM-1 TUG-3. The TL3M interfaces to an STM-1 or STS-3 SDH/SONET signal

UPD 056

Abstract: CBAW
Contextual Info: ASPEN Express Device DATA SHEET PRODUCT PREVIEW FEATURES DESCRIPTION The ASPEN Express device is a single-chip solution for implementing cost-effective ATM multiplexing and switching systems, based on the CellBus architecture. Such systems are constructed from a number of CUBIT-3, CUBIT-Pro,