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    SRAM 54-PIN TSOP

    Abstract: No abstract text available
    Text: PRELIMINARY CY14B104L/CY14B104N 4-Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns and 25 ns access times • Internally organized as 512K x 8 or 256K x 16 • Hands-off automatic STORE on power down with only a small capacitor • STORE to QuantumTrap nonvolatile elements is initiated


    Original     		PDF CY14B104L/CY14B104N 8/256K CY14B104L/CY14B104N to10ns to15ns SRAM 54-PIN TSOP

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CY14E104K/CY14E104M 4-Mbit 512K x 8 / 256K x 16 nvSRAM with Real-Time-Clock Features • 15 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14E104K) or 256K x 16 (CY14E104M) ■ Hands off automatic STORE on power down with only a small


    Original     		PDF CY14E104K/CY14E104M CY14E104K) CY14E104M)

    TSOP II 54

    Abstract: TSOP 48 thermal resistance junction to case TSOP 48 thermal resistance TSOP 54 thermal resistance
    Text: PRELIMINARY CY14B104L, CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns, 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off automatic STORE on power down with only a small


    Original     		PDF CY14B104L, CY14B104N 8/256K CY14B104L/CY14B104N TSOP II 54 TSOP 48 thermal resistance junction to case TSOP 48 thermal resistance TSOP 54 thermal resistance

    Untitled

    Abstract: No abstract text available
    Text: CY14B104L, CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 20 ns, 25 ns, and 45 ns Access Times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off Automatic STORE on power down with only a small


    Original     		PDF CY14B104L, CY14B104N 8/256K CY14B104L/CY14B104N

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CY14B104L, CY14B104N 4-Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off automatic STORE on power down with only a small


    Original     		PDF CY14B104L, CY14B104N 8/256K CY14B104L) CY14B104N) CY14B104L/CY14B104N

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CY14B104L, CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off automatic STORE on power down with only a small


    Original     		PDF CY14B104L, CY14B104N 8/256K CY14B104L/CY14B104N

    TSOP 54 Package

    Abstract: CY14B104L CY14B104N
    Text: CY14B104L, CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 20 ns, 25 ns, and 45 ns Access Times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off Automatic STORE on power down with only a small


    Original     		PDF CY14B104L, CY14B104N 8/256K CY14B104L) CY14B104N) CY14B104L/CY14B104N TSOP 54 Package CY14B104L CY14B104N

    CY14B104L

    Abstract: CY14B104N
    Text: PRELIMINARY CY14B104L, CY14B104N 4-Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off automatic STORE on power down with only a small


    Original     		PDF CY14B104L, CY14B104N 8/256K CY14B104L) CY14B104N) CY14B104L/CY14B104N CY14B104L CY14B104N

    TSOP 54 PIN

    Abstract: TSOP 54 Package CY14B104L CY14B104N
    Text: PRELIMINARY CY14B104L, CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns, 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off automatic STORE on power down with only a small


    Original     		PDF CY14B104L, CY14B104N 8/256K CY14B104L) CY14B104N) CY14B104L/CY14B104N TSOP 54 PIN TSOP 54 Package CY14B104L CY14B104N

    TSOP 54 Package

    Abstract: TSOP 48 thermal resistance TSOP 54 PIN TSOP 54 Package used in where TSOP II 54 TSOP II 54 Package
    Text: PRELIMINARY CY14B104L/CY14B104N 4-Mbit 512K x 8/256K x 16 nvSRAM Feature Functional Description • 15 ns, 25 ns, and 45 ns access times • Internally organized as 512K x 8 or 256K x 16 • Hands-off automatic STORE on power down with only a small capacitor


    Original     		PDF CY14B104L/CY14B104N 8/256K CY14B104L/CY14B104N to10ns to15ns TSOP 54 Package TSOP 48 thermal resistance TSOP 54 PIN TSOP 54 Package used in where TSOP II 54 TSOP II 54 Package

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CY14E104K/CY14E104M 4 Mbit 512K x 8 / 256K x 16 nvSRAM with Real-Time-Clock Features • 15 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14E104K) or 256K x 16 (CY14E104M) ■ Hands off automatic STORE on power down with only a small


    Original     		PDF CY14E104K/CY14E104M 44/54-pin CY14E104K) CY14E104M)

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CY14E104K/CY14E104M 4 Mbit 512K x 8 / 256K x 16 nvSRAM with Real-Time-Clock Features • 15 ns, 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14E104K) or 256K x 16 (CY14E104M) ■ Hands off automatic STORE on power down with only a small


    Original     		PDF CY14E104K/CY14E104M CY14E104K) CY14E104M)

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CY14B104L/CY14B104N 4-Mbit 512K x 8/256K x 16 nvSRAM Feature Functional Description • 15 ns, 25 ns, and 45 ns access times • Internally organized as 512K x 8 or 256K x 16 • Hands-off automatic STORE on power down with only a small capacitor


    Original     		PDF CY14B104L/CY14B104N 8/256K CY14B104L/CY14B104N to10ns to15ns