TOP 256 YN Search Results

OEB47

Contextual Info: MITSUBISHI DIGITAL ASSP M66221SP/FP 256 X 9-BIT MAIL-BOX DESCRIPTION PIN CONFIGURATION (Top view) The M66221 is a mail box that incorporates a complete CMOS shared memory cell of 256 x 9-bit configuration using high-performance silicon CHIP SELECT INPUT CSA -»

LT 7201

Abstract: AS221AF LT 7202
Contextual Info: SN74ACT7200L, SN74ACT7201 LA, SN74ACT7202LA 256 x 9, 51 2 x 9, 1 024 x 9 AS YN CH RO N O US FIRST-IN, FIRST-OUT MEMORIES S C A S 221A - FEBRUARY 1993 - REVISED SEPTEMBER 1995 • DV OR NP PACKAGE TOP VIEW R e a d s and Wr ites Can B e A s y n c h r o n o u s

M514800A

Abstract: m514800
Contextual Info: HM514800A/AL Series HM51S4800A/AL Series Preliminary 52 4,28 8-w o rd x 8 -b it D y n a m ic R a n d o m A c ce ss M em ory T he H itach i H M 514800A are C M O S d ynam ic R A M o rg a n iz e d as 5 2 4 ,2 8 8 -w o rd x 8 -b it. HM 514800A have realized higher density, higher

Contextual Info: iw VITELIC V 53C 256 FAMILY HIG H PERFORMANCE, LOW POWER 2S 6K X 1 B IT FAST PAGE MODE CMOS D YN AM IC RAM f HIGH PERFORMANCE V53C256 70/70L 80/80L Max. RAS Access Time, tRAC 70 ns 80 ns 100 ns 120 ns Max. Column Address Access Time, tQAA 35 ns 40 ns 45 ns

MC68010

Abstract: Motorola B13 mc68eco MC68030 MC12078 MC68EC040R33 TEA 1732
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1.3GHz Prescaler MC12078 The MC12078 is a divide by 256 prescaler. Typical frequency s yn th e sis a p p lica tio n s inclu d e e lctro n ica lly tuned T V /C A T V and com m unication systems as well as instrumentation.

top 256 yn

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1.3GHz Prescaler MC12078 The MC12078 is a divide by 256 prescaler. Typical frequency s yn th e sis a p p lica tio n s in clu d e e lc tro n ic a lly tu n e d TV /C A T V and com m unication systems as well as instrumentation.

am8085

Abstract: Dynamic Memory Refresh Controller MOS RAMs AmZ8
Contextual Info: AmZ8164 D ynam ic M em ory Controller ADVANCED INFORMATION DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • Dynamic Memory Controller for 16K and 64K MOS dynamic RAMs • 8-Bit Refresh Counter for refresh address generation, has clear input and terminal count output

HM514102

Contextual Info: HM514102C/CL Series 4,194,304-w ord x 1 -b it D ynam ic R andom A ccess M em ory Rev. 0.0 O ct. 20, 1994 HITACHI The Hitachi HM514102C/CL is a CMOS dynamic R A M o rg a n iz e d 4 ,1 9 4 ,3 0 4 -w o rd x 1-bit. H M 514102C /C L has re a liz e d h ig h er den sity ,

Contextual Info: HM514400C/CL Series 1,048,576-w ord x 4-b it D ynam ic Random Access M em ory HITACHI The H itachi H M 514400C is a CM OS dynam ic R A M o rg a n iz e d 1,0 4 8 ,5 7 6 -w o rd x 4 -b it. HM 514400C has realized higher density, higher performance and various functions by employing

Contextual Info: HM514800A/AL Series HM51S4800A/AL Series Preliminary 5 2 4,28 8-w o rd x 8 -b it D ynam ic R a nd o m A c c e s s M em ory T he H ita c h i H M 5 I 4 8 0 0 A RAM o rg a n iz e d as ¿ire C M O S d y n a m i c 5 2 4 ,2 8 8 -w o rd Features x 8 -h it. H M 5 I 4 8 0 0 A have re a liz e d h i g h e r dens ity, h ig h e r

Contextual Info: KM418C256/L/SL CMOS DRAM 256Kx 18 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION • P erfo rm ance range: Th e S am su ng K M 41 8 C 2 5 6 /L /S L is a C M O S high speed 262,144 bit x 18 D ynam ic R andom A ccess M em o ry. Its K M 418C 256/L/S L-7

V53C464-80

Abstract: V53C464-80L V53C464
Contextual Info: 9502310 VIT EL IC CORP 98D 00380 V I T E L I C CO RP Tfl jr “ VITELIC D - T-Vé-23-Z7 DE ^ TSD5310 DODGBflD S | VS3C464 FAMILY HIGH PERFORMANCE, LOW POWER 64 K X 4 B IT FAST PAGE M ODE CMOS D YN A M IC RAM HIGH PERFORMANCE V53C464 70/70L 10/10L 12/12L 80 ns

HM514410

Contextual Info: HM51441OB/BL Series 1,048,576-word x 4-bit D ynam ic R A M The Hitachi H M ? 14 4 1O B/BL is a C M O S dynamic Ordering Information R A M organi/.ed I .04K .576-w ord x 4-hit. H M 5 14 4 1O B / B L has realized h ig h er density, higher perform ance and various functions by

Contextual Info: HM514260A/AL-6R Series HM51S4260A/AL-6R Series Preliminary 262,144-w ord x 16-bit D ynam ic Random Access Mem ory U • IT A P U I Rev. 0.1 May. 3 1 ,1 9 9 4 ■ ■ T h e Hitachi H M 5 1 4 2 6 0 A / A I . are C M O S d y n am ic R A M o r g a n i z e d as 2 6 2 , 1 4 4 - w o r d x 1 6 - b i t .

Contextual Info: MOSEL V i T E L i C V53C8125L ULTR A -H IG H PERFORM ANCE, 3.3 VO LT 128K X 8 B IT F A S T PA G E M O D E CM OS D YN A M IC R A M HIGH PERFORMANCE P R ELIM IN A R Y 60 Max. RAS Access Time, tp^c 60 ns Max. Column Address Access Time, (tCAA) 30 ns Min. Fast Page Mode Cycle Time, (tPC)

Contextual Info: PRELIMINARY M O SE L V IT E L IC V53C8125H U LTRA-H IG H P E R FO R M A N C E , 128K X 8 F A S T PAGE M O D E CM OS D YNAM IC R A M HIGH PERFORMANCE 35 40 45 50 35 ns 40 ns 45 ns 50 ns 18 ns 20 ns 22 ns 24 ns in. Fast Page Mode Cycle Time, tpc 21 ns 23 ns

EZ613

Abstract: MSM51C256-10 MSM51C256 MSM51C256RS
Contextual Info: y - y . . O K I SEMICONDUCTOR GROUP O K I semiconductor_ T -V * MSM51C256 2 6 2 ,1 4 4 W ORD X1-BITS D YN A M IC RAM GENERAL DESCRIPTION The MSM51C256 is a new generation dynamic RAM organized as 262,144 words by 1 bit. The technology used to fabricate the MSM51C256 is OKI's CMOS silicon gate process technology. The

uVGA

Abstract: microVGA CP2102 AVR rgb ftdi spi example 320X240
Contextual Info: USERS MANUAL µVGA PICASO MD1 Tiny VGA Graphics Controller QVGA, VGA, SVGA Revision 1.2 4D Systems PROPRIETORY INFORMATION The information contained in this document is the property of 4D Systems Pty. Ltd., and may be the subject of patents pending or granted, and must not be copied or disclosed with out

HYUNDAI i10

Contextual Info: PRELIMINARY HY51C464 HYUNDAI SEMICONDUCTOR 6 5 ,5 3 6 x4-Bit CMOS D ynam ic RAM AUGUST 1986 Oov,cd- The HY51C464 offers a m axim um standby current of 100 ft A w hen RAS ? Vdd—0.5V. During standby i.e. refresh only cycles , the refresh period can be extended to 32 ms to reduce the total current re­

ZL68

Contextual Info: DUAL 256/512/1024x36 CMOS SyncFlFO FEATURES: ADVANCED INFORMATION IDT723622 IDT723632 IDT723642 space-saving 120-pin Thin Quad Flatpack PF • Free-running CLKA and CLKB may be asynchronous or coincident • Two independent clocked FIFOs buffering data in oppo­

Contextual Info: D U AL D U AL D U AL D U AL C M O S S yncFlFO 256 x 9, D U AL 512 x 9, 1,024 x 9, D U AL 2,048 x 9, 4 ,096 x 9, D U AL 8,192 x 9 Each of the two FIFOs designated FIFO A and FIFO B contained In the IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port

Contextual Info: KM44C4110A/AL/ALL/ASL CMOS DRAM 4M x 4 Bit CMOS Dynamic RAM with Fast Page Mode Write Per Bit Mode FEATURES GENERAL DESCRIPTION • Performance range: The S am sung K M 44 C 4 110 A /A L/A LL /A S L is a high speed C M O S 4 ,1 9 4 ,3 0 4 b i t x 4 D ynam ic R andom

14241

Abstract: TO63 package CY7C4201 CY7C4211 CY7C4221 CY7C4231 CY7C4241 CY7C4251 CY7C42X1 CY7C4421
Contextual Info: fax id: 5409 •>* : CY7C4421/4201 /4211/4221 CY7C4231/4241/4251 .6 4 /2 5 6 /5 1 2 /1 K /2K /4K /8K x 9 S ynch ro no us FIFO s Functional Description Features • High-speed, low-power, first-in, first-out FIFO memories • 6 4 x 9 (CY7C4421) • 256 x 9 (CY7C4201)

ADU01

Abstract: Intel P55 Chipset D31CD
Contextual Info: — ^ C Y M 7 4 B P 5 4 CYM 74P54/55 ^ l r t î m n r n P R E L IM IN A R Y . n wm W U ir K fc b b C Y M 7 4 S P 5 4 /5 5 — Intel 82430NX Chipset Level II Cache Module Family Feat ures • Pi n- compat i bl e secondary cache mo d ul e family • As yn ch r o no u s CYM7 4BP5 4 , sync h r o no us pipelined