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    SCANSTA111

    Abstract: STA111
    Text: SCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 JTAG Port General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board


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    PDF SCANSTA111 SCANSTA111 IEEE1149 STA111

    CDC318

    Abstract: No abstract text available
    Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps


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    PDF CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin CDC318

    Untitled

    Abstract: No abstract text available
    Text: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in


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    PDF CDCLVD2108 SCAS905C EIA/TIA-644A 48-Pin

    Untitled

    Abstract: No abstract text available
    Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps


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    PDF CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin

    48-PIN

    Abstract: CDC318A CDC318ADL CDC318ADLG4
    Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications


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    PDF CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A CDC318ADL CDC318ADLG4

    Untitled

    Abstract: No abstract text available
    Text: SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 JTAG Port Check for Samples: SCANSTA111 FEATURES DESCRIPTION • The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The


    Original
    PDF SCANSTA111 SNLS060K SCANSTA111

    Untitled

    Abstract: No abstract text available
    Text: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in


    Original
    PDF CDCLVD2108 SCAS905C EIA/TIA-644A 48-Pin CDCLVD2108m/clocks

    Untitled

    Abstract: No abstract text available
    Text: SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 JTAG Port Check for Samples: SCANSTA111 FEATURES DESCRIPTION • The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The


    Original
    PDF SCANSTA111 SNLS060K SCANSTA111

    48-PIN

    Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
    Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications


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    PDF CDC318A 18LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR

    K3638

    Abstract: 4Y04
    Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications


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    PDF CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin K3638 4Y04

    Untitled

    Abstract: No abstract text available
    Text: CDCLVD1216 www.ti.com SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011 2:16 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1216 FEATURES 1 • • • • • • • • • • • • 2:16 Differential Buffer Low Additive Jitter: <300 fs RMS in


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    PDF CDCLVD1216 SCAS900B EIA/TIA-644A 48-Pin

    Untitled

    Abstract: No abstract text available
    Text: CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • • • • • • • • • • • • Dual 1:8 Differential Buffer Low Additive Jitter <300 fs RMS in


    Original
    PDF CDCLVD2108 SCAS905C EIA/TIA-644A 48-Pin

    48-PIN

    Abstract: CDC318A
    Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications


    Original
    PDF CDC318A 18LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A

    STA111

    Abstract: SCANSTA111
    Text: SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 JTAG Port • Mode Register0 allows local TAPs to be bypassed, General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved


    Original
    PDF SCANSTA111 SCANSTA111 STA111

    CDC318

    Abstract: CDC318DL CDC318DLR
    Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps


    Original
    PDF CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin CDC318 CDC318DL CDC318DLR

    SCANSTA111

    Abstract: STA111
    Text: SCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 JTAG Port General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board


    Original
    PDF SCANSTA111 SCANSTA111 IEEE1149 STA111

    CDC318

    Abstract: No abstract text available
    Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps


    Original
    PDF CDC318 18-LINE SCAS587B 1-to-18 MIL-STD-883, 48-Pin CDC318

    3014 LED

    Abstract: MARKING CFK l1801-1 SVI 3003 W2T marking 103 c1k end of life car tyres T-17911 54ls162 jill2
    Text: MIL-M-38510/315C 17 Ja n u a r y 1984 SUPERSEDING M I L - M - 3 8 5 1 0 / 3 1 5B 16 April 1981 MILITARY MICROCIRCUITS, SPECIFICATION DIGITAL, T T L , COUNTERS, LOW-POWER MONOLITHIC T hi s s p e c i f i c a t i o n is a p p r o v e d ments and Agencies of th e


    OCR Scan
    PDF MIL-M-38510/315C MIL-M-38510/315B MIL-M-38510. 54LS163A 54LS19Ã MIL-M-38510/315C 5-040/A 3014 LED MARKING CFK l1801-1 SVI 3003 W2T marking 103 c1k end of life car tyres T-17911 54ls162 jill2

    marking code ADg

    Abstract: ic 76 adg l7 723 M/A relay lzl T7895 aos Lot Code Identification n7t marking iwatt marking
    Text: MIL-M-38510/520B 20 JUNE 1983 W L R S E DING-MIL-M-38510/520A 9 D e c e m b e r 1982 MILITARY MICROCIRCUITS, SPECIFICATION DIGITAL, MONOLITHIC N-CHANNEL, SILICON GATE 16-BIT M I C R O PR OC ES SO R T h i s s p e c i f i c a t i o n is a p p r o v e d f o r u s e b y all D e p a r t ­


    OCR Scan
    PDF MIL-M-38510/520B MIL-M-38510/520A 16-BIT MIL-M-38510. Z8001 Z8002 Z8001A Z8002A marking code ADg ic 76 adg l7 723 M/A relay lzl T7895 aos Lot Code Identification n7t marking iwatt marking

    Untitled

    Abstract: No abstract text available
    Text: M MOTOROLA M ilita ry 54L S 1 9 0 4-B it D ecad e Counter W ith M ode Control ELECTRICALLY TESTED PER: MIL-M-38510/31513 M T h e 5 4L S 1 9 0 is an a syn ch ro n o u s U P/D O W N B C D D ecade (8421) C o u n te r and th e 54LS191 is a syn chro n o us U P/D O W N M o du lo -16 B inary


    OCR Scan
    PDF MIL-M-38510/31513 54LS191

    hl43

    Abstract: TIL413 IZ6 data sheet PJ 3139 B38G 2901c marking AYB
    Text: I QUALI FI CAI 1ÜTTI I REQUIREMENTS I REMOVED M I I MILITARY MICROCIRCUITS, DIGITAL, T h i s s p e c i f i c a t i o n is ments and Agencies should be FOUR-31T noted that previous MICROPROCESSOR Scope. This reflected approved of the f o r u s e by Department


    OCR Scan
    PDF MIL-M-38510/440B M1L-M-38510, HIL-H-38510/440C hl43 TIL413 IZ6 data sheet PJ 3139 B38G 2901c marking AYB

    Untitled

    Abstract: No abstract text available
    Text: M MOTOROLA M ilitary 54LS190 4 -B it D ecade C o u n ter W ith M ode C ontro l ELECTRICALLY TESTED PER: MIL-M-38510/31513 The 54LS190 is an a synch ro n ou s UP/DOWN BCD Decade (8421) C ounter and th e 54LS191 is a syn ch ro n o u s UP/DOWN M o d u lo -1 6 B inary


    OCR Scan
    PDF MIL-M-38510/31513 54LS190 54LS191

    54LS190

    Abstract: No abstract text available
    Text: g M ilita ry 5 4 L S 1 9 0 MOTOROLA 4-B it D ecad e C ounter W ith M ode Control ELECTRICALLY TESTED PER: MIL-M-38510/31513 M The 54LS190 is an asynchronous UP/DOWN BCD Decade (8421) Counter and the 54LS191 is a synchronous UP/DOWN Modulo-16 Binary Counter.


    OCR Scan
    PDF MIL-M-38510/31513 54LS190 54LS191 Modulo-16 PLH11 PHL12

    Untitled

    Abstract: No abstract text available
    Text: M M O T O R O L A M ilitary 54LS191 Synchronous 4-Bit Up/Down Binary Counter With Mode Control ELECTRICALLY TESTED PER: MIL-M-38510/31509 M T h e 54LS191 is a syn ch ro n o u s U P/D O W N M o du lo -16 Binary C ounter. S ta te ch a n g e s of the co un ters are syn chro n o us w ith the


    OCR Scan
    PDF MIL-M-38510/31509 54LS191 tPHL15 PLH12 PLH12