TPL 624 Search Results

FUNCTIONAL APPLICATION OF 74LS148

Abstract: pin diagram of ic 74ls148 HD7x
Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M 74H C 148P /FP /D P 8 -L IN E TO 3 -L IN E P R IO R IT Y ENCODER DESCRIPTION T h e M 7 4 H C 1 4 8 is a sem iconductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of an 8 -lin e binary octal e n c o d e r with priority.

M4066BP

Abstract: M4016BP M4066BFP IVI4066BP IVS4066BP 109fl M4016 10KN 109fi
Contextual Info: M 4066BP SVS4066BFP •« -í • •¡■y v . QUADRUPLE B ILA TE R AL SW ITCH 6249826 MITSUBISHI ^ DESCRIPTION ELEK LINEA R / The M4066BP is a semiconductor integrated circuit consist­ 8 OC 0 9 1 1 7 D PIN CONFIGURATION (TOP VIEW) ~ ing of four independent bilateral analog switches.

ci la 7610

Abstract: tpl 624
Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC251P/FP/DP 8 -IN P U T DATA S E L E C T O R /M U L T IP L E X E R W IT H 3 -S T A T E O U TPU TS DESCRIPTION T h e M 7 4 H C 2 5 1 is a sem iconductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of an 8 -lin e to 1 -lin e data s e le c to r/m u ltip le x e r with

Contextual Info: M IT S U B IS H I <DIGITAL ASSP> M 7 4 H C T 2 4 1 -1 P /F P OCTAL 3-S TA T E N O N IN VE R TIN G B U F F E R /L IN E D R IV E R /L IN E R E C E IV E R W IT H L S T T L -C O M P A T IB L E IN P U T S DESCRIPTION PIN CONFIGURATION TOP VIEW T h e M 7 4 H C T 2 4 1 -1 is an in teg ra te d circuit chip consisting

Contextual Info: HCMP96850 S P 7 SIGNAL PROCESSING TECHNOLOGIES SINGLE ULTRAFAST VOLTAGE COMPARATOR FEATURES APPLICATIONS • • • • • • • • • • Propagation Delay of 2.4 ns typ Propagation Delay Skew <300 ps Low Offset ±3 mV Latch Control High Speed Instrumentation, ATE

Contextual Info: SPT S/GA/AL PßOCESSWG TECHNOLOGIES H C M P9 6 8 5 Ö SINGLE ULTRA FAST VOLTAGE COMPARATOR FEATURES APPLICATIONS • • • • • • • • • • Propagation Delay of 2.4 ns typ Propagation Delay Skew <300 ps Low Offset ±3 mV Latch Control High Speed Instrumentation, ATE

toko delay lines dip

Abstract: toko delay lines
Contextual Info: TOKO AMERICA/ SIGNAL LEE ]> • 8248^17 0 D0244fl ^53 H S SPT SPT9689 DUAL ULTRA-FAST VOLTAGE COMPARATOR SIGNAL PROCESSING TECHNOLOGIES FEATURES APPLICATIONS • • • • • • • • • • • • • • • 650 ps Propagation Delay 100 ps Propagation Delay Variation

Contextual Info: MITSUBISHI -CDGTL LOGIC} TI d F b H ^ a S ? Í T o D ia s n M IT S U B IS H I ASTTLs it\^s . t ws l5« w" rt" M 74A S3 73P se*c'l' «G^ ° c s, e ^ T - V O 1,0« So^ a - o i- c S ’ 0<n OCTAL D -T Y P E TRANSPARENT LATCH W IT H 3-STA TE O UTPUT (NO NINVER TED

tdc 310

Abstract: HP9000 RS6000 tpl 624
Contextual Info: 0.25µm ASICs MG113P/114P/115P/73P/74P/75P FAMILY LISTING 60µm Staggered PAD products SOG Base Array MG11xP14 MG11xP18 MG11xP22 MG11xP28 No. of Raw Gates MG113P/73P Family 3LM Usable Gates MG114P/74P Family 4LM Usable Gates MG115P/75P Family 5LM Usable Gates

367FP

Contextual Info: MITSUBISHI HIGH SPEED CMOS M74HC367P/FP/DP HEX 3-STATE NONINVERTING B U FFER WITH SEPAR ATE 2-BIT AND 4-BIT SECTIONS DESCRIPTION The M74HC367 is a semiconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW sisting of six buffers with 3-state noninverted outputs, the 4bit and 2-bit sections having common enable inputs.

M74HC126

Abstract: M74HC12
Contextual Info: M ITSU B ISH I HIGH SPEED CMOS M 74H C 126P/FP/D P Q UADRUPLE 3-S TA T E N O N IN VERTIN G B U FF E R DESCRIPTION The M 74H C 126 is a sem iconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW sisting of four buffers each w ith 3-state noninverted outputs

74ALS576

Contextual Info: -O S ' & MITSUBISHI ALSTTLs M 74A LS 576A P o80 Í < ° o ^ <'96 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP 3AÍITH 3-STATE OUTPUT INVERTED » S * ’ “'* 6249827 MITSUBISHI CDGTL LO GI C) DESCRIPTION 9 1D 12604 D PIN CONFIGURATION (TOP VIEW) OUTPUT CONTROL 'oc - E

74HC574P

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS \VAV M 74H C 574P /FP /D W P „ d t » " 0" _su'»'' OCTAL 3-S TA T E N O N IN VERTIN G D -T Y P E F L IP -F L O P DESCRIPTION The M74HC574 is a semiconductor integrated circuit con­ sisting of eight edge-triggered D-type flip-flops with 3-state

M74HC574

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M 74H C 564P /F P /D W P ^\0"' t\oa s"’“ ' ; ° " CV C" OCTAL 3-S TA T E IN V E R TIN G D -T Y P E F L IP -F L O P DESCRIPTION The M 74H C 564 is a sem iconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW sisting of eigh t e d g e -trig g e re d D -type flip -flo p s w ith 3-state

Contextual Info: HB286015C1 Series 15 Mega Byte CompactFlash HITACHI ADE-203-624A Z Rev. 1.0 Feb. 28, 1997 Description HB286015C1 is a 15 Mega bytes CompactFlash™. This card complies with CompactFlash™ specification, and is suitable for the usage of data storage memory medium for PC or any other electric equipment and

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC257P/FP/DP Q UADRUPLE 2 -IN P U T DATA S E L E C T O R /M U L T IP L E X E R W ITH 3-S TA T E O U TPU TS DESCRIPTION The M 74H C 257 is a sem iconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW sisting of four 2-line to 1 -line data sele cto rs/m u ltip le xe rs

M74HC540P

Abstract: 74HC540FP
Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC540P/FP/DWP OCTAL 3-S TA T E IN V E R TIN G B U F F E R /L IN E D R IV E R /L IN E R E C EIVER DESCRIPTION T h e M 7 4 H C 5 4 0 is a sem ico nductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of 3 -s ta te inverting buffers each with eight in d e p e n ­

Contextual Info: MITSUBISHI <DIGITAL ASSP> M 74H C 138-1P /FP l-OF-8 D ECO D ER/D EM U LTIPLEXER DESCRIPTION T h e M 7 4 H C 1 3 8 -1 is a sem iconductor in teg ra te d circuit con­ PIN CONFIGURATION TOP VIEW sisting of a 3 -b it binary to 8 -lin e d e c o d e r/d e m u ltip le x e r with

tpl 624

Abstract: 74HC243P
Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M 74H C 243P /F P/DP QUADRUPLE 3-S TA TE NONINVERTING BUS TR A N S C E IVE R DESCRIPTION PIN CONFIGURATION TOP VIEW T h e M 7 4 H C 2 4 3 is a sem iconductor in teg rated circuit con­ sisting of four bus tran sceivers with noninverted outputs.

ic 74151

Abstract: ic 74163 oki cross MSM92RB01 MSM92RB02 msm32r0120 oki 82c54 82C54 oki of ic 74151 30R06
Contextual Info: MSM30R0000/MSM32R0000/MSM92R000 Second-Generation 0.5µm Sea of Gates and Customer Structured Arrays DESCRIPTION Oki's second-generation 0.5µ m ASIC products are available in both Sea Of Gates SOG and Customer Structured Array (CSA) architectures. The MSM30R Series, MSM32R Series, and MSM92R Series all offer

Contextual Info: DATA SHEET O K I A S I C P R O D U C T S MG113P/114P/115P/73P/74P/75P 0.25µm Sea of Gates and Customer Structured Arrays March 1998 MG113P/114P/115P/73P/74P/75P 0.25µm Sea of Gates and Customer Structured Arrays DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit ASIC products are available in both Sea Of Gates

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC354P/FP/DWP ' 8 -IN P U T DATA S E L E C T O R /M U L T IP L E X E R >° .-e\X'c W ITH DATA AND ADDRESS LATCHES AND WITH 3-STATE OUTPUTS DESCRIPTION T h e M 7 4 H C 3 5 4 is a sem ico nductor in teg rated circuit con­

relay TRK 1703

Abstract: hall 04E trk 1703 TOP 242 PN relay TRK 1203 rda 1486 balanced modulator ic 1496 SX043 trk 1203 SX042
Contextual Info: SX041, SX042, SX043 User’s Manual WavePlex  Wireless Products Introduction April 1996 1.0 Introduction baseband circuitry needed to implement a radio, thus providing an economical solution to the extensive digital hardware requirements of high performance spread

Contextual Info: MITSUBISHI - - - Í D G T iT L O G I C } "il D È I ^24^027 DG12S71 □ ¥ MI T S UB I S H I — ASTTLs M 74AS1808P 91D 12 271 t ò ^ pa's<re 7~ ~93-/S D HEX 2-1NPUT AND DRIVER DESCRIPTION The M74AS1808P is a semiconductor integrated circuit consisting of six 2-input positive-logic AND buffer gates,