TPTO Search Results

12Represents

Contextual Info: REVISION B 15,90 PCB LAYDUT MODS-G-TPTOX-S r TYPE -G 13,80 PDSITIDNS/CDNTACTS —1 -TPTD 10 Pos/10 Con PLATING -G , 0 0 0 0 1 5 ' Au -H , 0 0 0 0 3 0 ' Au -E , 0 0 0 0 5 0 ' Au y SE E NOTE 2 SHIELD -S: Shielded DD NOT SCALE FROM THIS PRINT NOTES: 1,

ABB B50

Abstract: ABB B45 AMP147 7475A RCB35 b4599 IB39
Contextual Info: THIS DRAWING 15 UNPUBLISHED. SI C O P Y R IG H T RELEASED FOR PUBLICATION J BY AHP INCORPORATED.ALL RIGHTS RESERVED. 1997 THI 5 NOT PUSHED 1 PTTT LÖC 20.AUG ,1997 . 15 P ART REVISIONS TPTO1 DE5ÍRIÊTIÔN ltr No. 1 1 2 3 0 6 6 - 1 RELEA5ED F J O O - 1 188-97

Contextual Info: tPtoducti, 20 STERN AVE. SPRINGFIELD, NEW JERSEY 07081 U.SA TELEPHONE: 973 376-2922 (212)227-6005 FAX: (973) 376-8960 2N4150 silicon NPNTransiitor Hermetically scaled TO] metal cm Collector-Emitter Voltage Collector-Base Voltage Emitter-Base Voltage Collector Current, Continuous

Contextual Info: ^unL-Condaatoi tPtoduct*, {Jne. 20 STERN AVE SPRINGFIELD, NEW JERSEY 07081 TELEPHONE: 973 376-2922 (212)227-6005 FAX: (973) 376-8980 U.SA 2N3764 Polarity PNP Features: • • • General-purpose transistor for switching and amplifier applicatons. Housed in a TO-46 case.

Contextual Info: 273 54F/74F273 Connection Diagrams Octal D Flip-Flop The ' f e | | J h | j eight edge-triggered D-type flip-flops with individual D inputs rf|tptots. The common buffered Clock CP and Master Reset (MR) in p u t! Idfecifiandfreset (clear) all flip-flops simultaneously.

Contextual Info: ispLSI 2064E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect

Contextual Info: LeadFree a P ckage Options Available! ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay • IN-SYSTEM PROGRAMMABLE D0 C7 A1 ES

4032V

Abstract: DS1017 LC4032V-10TN48I 4512c application LC4256V-75TN176C marking 17Z 4000B AEC-Q100 DS1020 22z2
Contextual Info: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs Coolest Power May 2009 C Features Data Sheet DS1020 TM • Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction Tj

B272

Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

2096VE

Abstract: TQFP 128pin
Contextual Info: ispLSI 2192VL Functional Block Diagram — — — — — 8000 PLD Gates 96 I/O Pins, Nine Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic

Contextual Info: Preliminary TR3002 • Designed for Short-Range Wireless Data Communications · Supports RF Data Transmission Rates Up to 115.2 kbps · 3 V, Low Current Operation plus Sleep Mode 418.00 MHz Hybrid Transceiver · Stable, Easy to Use, Low External Parts Count

Contextual Info: TR3006HS • Designed for Short-Range Wireless Data Communications • Supports RF Data Transmission Rates Up to 115.2 kbps • 3 V, Low Current Operation plus Sleep Mode • Stable, Easy to Use, Low External Parts Count • Complies with Directive 2002/95/EC RoHS

LC1 D25 004

Abstract: stk 0241 LC1 D27 LC1 D10 LC1 D25 10 sft 43 MSM699210 LC1 D09 10 stk 022 stk 023
Contextual Info: O K I semiconductor MSM699210 HIGH PERFORMANCE DIGITAL SIGNAL PROCESSOR FAM ILY 1. GENERAL OUTLINE The M S M 6 9 9 2 1 0 is a DSP same in architecture as th e M S M 6 992, b u t has doub led th e in tern al m em o ry size and reduced th e nu m b er o f pins by shared use o f th e external

4032 k14

Abstract: 4512c PX6A10 4256b L5591 a/4032 k14 am 4512C LC45 4064C m6 pt80
Contextual Info: TM ispMACH 4000B/C Family 2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs December 2001 Data Sheet • Broad Device Offering Features • • • • ■ High Performance • fMAX = 350MHz maximum operating frequency • tPD = 2.5ns propagation delay

Contextual Info: Lattica ispLSI and pLSI 1032 ;Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers

Contextual Info: Lattice pLSI 1016/883 programmable Large Scale Integration High-Density Programmable Logic Features Functional Block Diagram • PROGRAMMABLE HIGH-DENSITY LOGIC — — — — — MIL-STD-883 Version of the pLS11016 High-Speed Global Interconnects 32 I/O Pins, Four Dedicated Inputs

Contextual Info: Lattice ispLSI and pLSI 1048E ; Semiconductor I Corporation High-Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC O u tpu t R outing Pool — 8,000 PLD Gates | | O u tpu t R outing Pool ü m u lü lü llS i!

Contextual Info: Lattice ispLSr 1016 H I Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs

Contextual Info: Lattice ispLSr 1024 H I Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 4000 PLD Gates — 48 I/O Pins, Six Dedicated Inputs

Contextual Info: Lattice ispLSr 1032 H I Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs

jat52

Abstract: TA-TSY-000191 PM5319 PM5319-NI PMC-2030860
Contextual Info: us t, 20 04 09 :2 1: 24 PM ARROW 622 ASSP Telecom Standard Product Data Sheet Released es da y, 10 Au g PM5319 gi es , In c. on Tu ARROW 622 Released Issue No. 2: July 2004 Do wn lo ad ed by Sc o tt E st es of i 2T ec h no lo ASSP Telecom Standard Product Data Sheet

Contextual Info: ispLSI 2096V 3.3V High Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

2096VE

Contextual Info: ispLSI 2192VL 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram — — — — — 8000 PLD Gates 96 I/O Pins, Nine Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State

lattice 1016-60LJ

Abstract: 5962-9476201MXC 1016-80lj 1016-60 1016-60LH ISPLSI 1016-60LJ Lattice 1016-80LJ 0123A-isp1016 ISP1016
Contextual Info: ispLSI 1016 Device Datasheet September 2010 All Devices Discontinued! Product Change Notifications PCNs have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes.