TSEV83102G0GL Search Results

TSEV83102G0GL

Abstract: 10 GSPS ADC JTS83102G0 TS81102G0 TS83102G0 TS83102G0CGL
Contextual Info: Released under NDA TS83102G0 MAIN FEATURES ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 10-bit resolution. 2 GSPS sampling rate. 3 GHz full power input bandwidth. Band flatness: ± 0.2 dB from DC up to 1.5 GHz . Very low input VSWR : 1.15 max from DC to 2GHz (packaged device).

Contextual Info: Features • Programmable DMUX Ratio: • • • • • • • • • • • • • • – 1:4: Data Rate Max = 1 Gsps – PD 8b/10b < 4.3/4.7 W (ECL 50Ω output) – 1:8: Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50Ω output) – 1:16 with 1 TS8388B or 1 TS83102G0 and 2 DMUX

porte logique

Abstract: porte logique and TS83084G0 circuit logique Transistor 8c4 TS83084G TS81102G0 TS83102G0 TS8388B TSEV8388G
Contextual Info: MAIN FEATURES ! Programmable DMUX ratio : 1:4 : Data rate max = 1 Gsps, PD 8b/10b < 4.3 / 4.7 W (ECL 50Ω output) 1:8 : Data Rate max = 2GSPS, PD (8b/10b)< 6 / 6.9 W (ECL 50Ω output) 1:16 with 1 TS8388B or 1 TS83102G0 and 2 DMUX. ! Parallel output mode.

TS83084G0

Abstract: CQFP68 TS81102G0 TS83102G0 TS8388B TSEV8388G
Contextual Info: Features • Programmable DMUX Ratio: • • • • • • • • • • • • • • – 1:4: Data Rate Max = 1 Gsps – PD 8b/10b < 4.3/4.7 W (ECL 50Ω output) – 1:8: Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50Ω output) – 1:16 with 1 TS8388B or 1 TS83102G0 and 2 DMUX