TTL 74LS 00 Search Results

74LS14 not gate

Abstract: 74LS14 74ls14 ttl ttl 74ls14 74LS14 DATA LS14 74LS13 TTL Schmitt-Trigger Inverters 751A-02 LS13
Contextual Info: MOTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN 54LS /74LS 13 and S N 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into

Altera EP1800

Abstract: EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
Contextual Info: EP1800 Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conventional and custom logic. Speed equivalent to 74LS TTL with 25 MHz clock rates. “Zero Power” typically 10/jA standby . Active power of 250 mW at 5 MHz.

DN74LS245

Contextual Info: DN74LS245 LS TTL DN74LS Series DN74LS245 ro 74LS^4-S' Octal Bus Transceivers with 3 -state Outputs P-3 • Description DN74LS245 contains eight bus transmitter/receiver circuits with non-inverted outputs. ■ Features • Bidirectional transfer or separation capability for two 8-bit

shiftregisters

Abstract: EP910 altera TTL library 74LS series logic gates 74LS EP1810 EP1810-45 EP610 PLE40 altera logicaps TTL library
Contextual Info: EP1810 Y 7 \ m HIGH PERFORMANCE 4 8 MACROCELL EPLD m 10 I U FEATURES GENERAL DESCRIPTION • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conven­ tional and custom logic. • Speed equivalent to 74LS TTL with 33 MHz clock

DN74LS290

Abstract: QD32
Contextual Info: LS TTL DN74LS Series DN74LS290 DN74LS290 N>74LSÌ.<ÌO Decade Counters • Description P-1 D N 74LS290 is an asynchronous decade counter w ith a directcoupled reset in p u t and nine direct-coupled set inputs. ■ Features • • • • • Direct-coupled reset input

Contextual Info: LS TTL DN74LS Series D N 74LS 136 DN74LS136 ro 7q. LS 2>£> Quad 2 - input E xclusive OR G ates with Open C ollector Outputs) • Description P-1 DN74LS136 contains four 2-input exclusive OR gate circuits w ith open collector o utputs. ■ Features • •

DN74LS113

Abstract: MA161 100 mhz trigger generator 0n74
Contextual Info: I DN74LS113 LS TTL DN74LS Series D N 74LS 113 Dual J-K Negative Edge-Triggered F lip -F lop s with Set I Description P-1 DN74LS113 contains two negative-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K, and direct-coupled set input terminals.

DN74LS245

Abstract: MA161
Contextual Info: DN74LS245 LS TTL DN74LS Series DN74LS245 ro 74LS^4-S' O ctal Bus T r a n sc e iv e r s w ith 3 -sta te O u tp u ts • Description P-3 D N 74LS245 contains eight bus transm itter/receiver circuits with non-inverted outputs. ■ Features • • • • •

74LS

Abstract: CD4015B CD4015BC CD4015BM J16A
Contextual Info: June 1996 CD4015BM/CD4015BC Dual 4-Bit Static Shift Register Features • W ide supply voltage range ■ High noise im m unity ■ Low pow e r TTL com patibility 3.0V to 18V 0.45 V DD typ. Fan o ut o f 2 driving 74L o r 1 driving 74LS ■ M edium speed operation

Contextual Info: R C H II- P S E M IC O N D U C T O R tm DM74AS240, 244 3-STATE Bus Driver/Receiver Features • Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Improved switching performance with less power dissipation compared with Schottky counterpart ■ Functional and pin compatible with 74LS and Schottky

Contextual Info: LS TTL DN74LS Series DN74LS95B DN74LS95B f^74ls?Sß 4-bit Parallel - Access Shift Registers • Description P-1 DN74LS95B is a 4-bit serial/parallel input to serial/parallel o u tp u t shift register. ■ Features • • • • • S ynchronous serial/parallel input to serial/parallel o u tput

Contextual Info: LS TTL DN74LS Series DN74LS393 DN74LS393 K>74LS Dual 4 - b i t Binary Counters • Description P-1 DN 74LS393 contains tw o asynchronous 4-bit binary hexa­ decim al co u n ter circuits w ith direct-coupled reset inputs. ■ Features • • • • Two circuits corresponding to LS93 and LS293 for high

MM74HC138M

Abstract: 74HC 74LS138 M16A M16D MM74HC138 MM74HC138MTC MM74HC138SJ MTC16 mm74hc138n
Contextual Info: s e m i c o n d u c t o r Revised February 1999 MM74HC138 3-to-8 Line Decoder General Description The d ecoder’s outputs can drive 10 low pow er S chottky TTL equivalent loads, and are functionally and pin equiva­ lent to the 74LS 138. All inputs are protected from dam age

Contextual Info: October 1987 Revised January 1999 S E M ¡ C O N D U C T O R TM Features • Wide supply voltage range: ■ High noise immunity: 3.0V to 15V 0.45 Vqq typ. ■ Low power TTL compatibility: or 1 driving 74LS ■ New formula: C in Farads) PW 0 ut = RC Fan out of 2 driving 74L

DN74LS241

Abstract: MA161
Contextual Info: LS TTL DN74LS Series D N 74LS 241 DN74LS241 ro 7 4 L S Ä 4 I Octal Buffers AND Line Drivers with 3 - s t a t e Outputs • Description P -3 D N 7 4 L S 2 4 1 con tain s tw o buffer b lo ck s, each w ith ind ep en dent ou tp u t-co n tro l inp uts co m m o n to fou r circuits and 3 -state

LC74HC03

Contextual Info: I A 7 X L U 7 4 • LC74HC03 t i 5: -, X •C M O S Q u a d M U 4 [ü î& o U o 2 K il N A NAND V - N O p e n D G a t D r a in V 2 - e h T ‘ t5V ififŒ , K ^ -C 7 S É « ?>. lOmA W t f - T v H u -< V i B / i / / • ' Wtë<r>TzV> ¿ if * T ^ 4. • LS-TTL{ 74LSÛ3 ¿ 1=] — fc? x g £ ä t, [5] — î#Îfê'C*> 4 . -> >; □ v , j % — h T ’ a -e A T Î j  S ' C J : 0 L S - T T U g ^

CI 74ls139

Abstract: 74ls Logic Family Specifications 74LS TTL 74LS257A 74S257 CD7193D N74S257AN N74S257D N74S257N S257
Contextual Info: NAPC/ SXGNETXCS Signetics S1E D • bbSBTHM 0050012 1 ■ 74LS257A, S257 Ti&h&f Data Selectors/Multiplexers Quad 2-Llne To 1-Line Data Selector/Multiplexer 3-State Product Specification Logic Products FEATURES TYPICAL PROPAGATION DELAY TYPE • M ultifunction capability

CI 74ls139

Contextual Info: H IE NAPC/ SIGNETI CS D • ^ 53*124 0050012 74LS257A, S257 Signetics 1 ■ T -i& h */ Data Selectors/Multiplexers Quad 2-Llne To 1-Line Data Selector/Multiplexer 3-State Product Specification Logic Products FEATURES TYPICAL PROPAGATION DELAY TYPE • Multifunction capability

rs flip-flop IC 7400

Abstract: 74ls105 TTL LS 7400 74LS series logic gates 7400 fan-out 74LS 3 input AND gate IC TTL 7400 schematic 74LS04 fan-out 74ls series logic family 90 watts inverter by 12v dc with 6 transisters
Contextual Info: GENERAL DESCRIPTION ABSOLUTE MAXIMUM RATINGS Ovar operating free-air temper­ ature range unless otherwise noted Supply Voltage Vq c (See Note 1) Input Voltage V|n (See Note 1) Interemitter Voltage (See Note 2) Resistor Node Voltage, 54121, 74121 (See Note 1)

LT 5216

Abstract: ic 74132 LT 5212 74132 LT 5215 f 74132 74132 data LS132 ls132 equivalent TTL 74LS 00
Contextual Info: 74132, LS132 Signetics Schmitt Triggers Quad 2-Input NAND Schmitt Trigger Product Specification Logic Products The '132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming

74xx151

Abstract: 74XX08 TTL 74XX04 74XX00 74xx161 74XX139 74xx04 TTL 74XX00 74XX174 74XX374
Contextual Info: National Semiconductor Application Note 319 Larry Wakeman June 1983 The MM54HC MM74HC family of high speed logic components provides a combination of speed and power characteristics that is not duplicated by bipolar logic families or any other CMOS family This CMOS family has operating

Motorola 74LS

Abstract: 74ls123
Contextual Info: M M O T O R O L A DESCRIPTION - - These d-c triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used w ith

74xx04

Abstract: 74XX08 74XX00 74xx151 74xx161 TTL 74XX04 CMOS TTL Logic Family Specifications 74xx139 74als power consumption 74XX374
Contextual Info: Fairchild Semiconductor Application Note 319 June 1983 The MM54HC/MM74HC family of high speed logic components provides a combination of speed and power characteristics that is not duplicated by bipolar logic families or any other CMOS family. This CMOS family has operating speeds

LM 7410

Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns