TTL 74LS 00 Search Results

Altera EP1800

Abstract: EP1800 JEDEC FORMAT EP1800 altera logicaps TTL library SCHEMA PA BUILT UP EP1800 LOGIC DIAGRAM ep18001
Contextual Info: EP1800 Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conventional and custom logic. Speed equivalent to 74LS TTL with 25 MHz clock rates. “Zero Power” typically 10/jA standby . Active power of 250 mW at 5 MHz.

shiftregisters

Abstract: EP910 altera TTL library 74LS series logic gates 74LS EP1810 EP1810-45 EP610 PLE40 altera logicaps TTL library
Contextual Info: EP1810 Y 7 \ m HIGH PERFORMANCE 4 8 MACROCELL EPLD m 10 I U FEATURES GENERAL DESCRIPTION • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conven­ tional and custom logic. • Speed equivalent to 74LS TTL with 33 MHz clock

DN74LS290

Abstract: QD32
Contextual Info: LS TTL DN74LS Series DN74LS290 DN74LS290 N>74LSÌ.<ÌO Decade Counters • Description P-1 D N 74LS290 is an asynchronous decade counter w ith a directcoupled reset in p u t and nine direct-coupled set inputs. ■ Features • • • • • Direct-coupled reset input

DN74LS113

Abstract: MA161 100 mhz trigger generator 0n74
Contextual Info: I DN74LS113 LS TTL DN74LS Series D N 74LS 113 Dual J-K Negative Edge-Triggered F lip -F lop s with Set I Description P-1 DN74LS113 contains two negative-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K, and direct-coupled set input terminals.

DN74LS245

Abstract: MA161
Contextual Info: DN74LS245 LS TTL DN74LS Series DN74LS245 ro 74LS^4-S' O ctal Bus T r a n sc e iv e r s w ith 3 -sta te O u tp u ts • Description P-3 D N 74LS245 contains eight bus transm itter/receiver circuits with non-inverted outputs. ■ Features • • • • •

Contextual Info: R C H II- P S E M IC O N D U C T O R tm DM74AS240, 244 3-STATE Bus Driver/Receiver Features • Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Improved switching performance with less power dissipation compared with Schottky counterpart ■ Functional and pin compatible with 74LS and Schottky

Contextual Info: LS TTL DN74LS Series DN74LS95B DN74LS95B f^74ls?Sß 4-bit Parallel - Access Shift Registers • Description P-1 DN74LS95B is a 4-bit serial/parallel input to serial/parallel o u tp u t shift register. ■ Features • • • • • S ynchronous serial/parallel input to serial/parallel o u tput

Contextual Info: LS TTL DN74LS Series DN74LS393 DN74LS393 K>74LS Dual 4 - b i t Binary Counters • Description P-1 DN 74LS393 contains tw o asynchronous 4-bit binary hexa­ decim al co u n ter circuits w ith direct-coupled reset inputs. ■ Features • • • • Two circuits corresponding to LS93 and LS293 for high

Contextual Info: October 1987 Revised January 1999 S E M ¡ C O N D U C T O R TM Features • Wide supply voltage range: ■ High noise immunity: 3.0V to 15V 0.45 Vqq typ. ■ Low power TTL compatibility: or 1 driving 74LS ■ New formula: C in Farads) PW 0 ut = RC Fan out of 2 driving 74L

XIFG

Contextual Info: P ANASONIC INDL/ELEK ÌICJ 72 69328.52 PANASONIC DE | >,*132055 □ □ □ 7 2 1 cì 1 IN D L *E L E C T R O N IC 72 LS TTL DN 74LS^'J-X C ' 0 7 2 1 9 . O 7 t/ 6 ' 0 9 ~0 J DN74LS295B/DN74LS295BS DN74LS295B/DN74LS295BS 4“ bit Bidirectional Universal Shift R egister

DN74LS241

Abstract: MA161
Contextual Info: LS TTL DN74LS Series D N 74LS 241 DN74LS241 ro 7 4 L S Ä 4 I Octal Buffers AND Line Drivers with 3 - s t a t e Outputs • Description P -3 D N 7 4 L S 2 4 1 con tain s tw o buffer b lo ck s, each w ith ind ep en dent ou tp u t-co n tro l inp uts co m m o n to fou r circuits and 3 -state

LC74HC03

Contextual Info: I A 7 X L U 7 4 • LC74HC03 t i 5: -, X •C M O S Q u a d M U 4 [ü î& o U o 2 K il N A NAND V - N O p e n D G a t D r a in V 2 - e h T ‘ t5V ififŒ , K ^ -C 7 S É « ?>. lOmA W t f - T v H u -< V i B / i / / • ' Wtë<r>TzV> ¿ if * T ^ 4. • LS-TTL{ 74LSÛ3 ¿ 1=] — fc? x g £ ä t, [5] — î#Îfê'C*> 4 . -> >; □ v , j % — h T ’ a -e A T Î j  S ' C J : 0 L S - T T U g ^

rs flip-flop IC 7400

Abstract: 74ls105 TTL LS 7400 74LS series logic gates 7400 fan-out 74LS 3 input AND gate IC TTL 7400 schematic 74LS04 fan-out 74ls series logic family 90 watts inverter by 12v dc with 6 transisters
Contextual Info: GENERAL DESCRIPTION ABSOLUTE MAXIMUM RATINGS Ovar operating free-air temper­ ature range unless otherwise noted Supply Voltage Vq c (See Note 1) Input Voltage V|n (See Note 1) Interemitter Voltage (See Note 2) Resistor Node Voltage, 54121, 74121 (See Note 1)

74xx04

Abstract: 74XX08 74XX00 74xx151 74xx161 TTL 74XX04 CMOS TTL Logic Family Specifications 74xx139 74als power consumption 74XX374
Contextual Info: Fairchild Semiconductor Application Note 319 June 1983 The MM54HC/MM74HC family of high speed logic components provides a combination of speed and power characteristics that is not duplicated by bipolar logic families or any other CMOS family. This CMOS family has operating speeds

74ls112 pin diagram

Abstract: 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
Contextual Info: 7 4 LS1 1 2 , S 1 1 2 Flip-Flops S ig n e t ic s Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and_Reset inputs. The Set So and Reset (R d) inputs, when LOW,

74LS139

Abstract: S139
Contextual Info: 74LS139, S139 Signetìcs Decoders/Demultiplexers Dual 1-of-4 D e c o d e r/D e m u ltip le x er Product Specification Logic Products FEA TUR ES • Demultiplexing capability • Two independent 1-of-4 decoders • Multifunction capability • Replaces 9321 and 93L21 for

TTL 7411

Abstract: PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10
Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification I TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA

74LS05 equivalent

Abstract: 7405 signetics 7405 74LS05 function table
Contextual Info: Signetics I 7405, LS05, S05 Inverters Hex Inverter Open Collector Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7405 40ns (tPLH) 8ns (tpHL) 12mA 74LS05 17ns (tPUH) 15ns (tpHu) 2.4mA 74S05 5ns (tpLH) 4.5ns (tpHL)

74LS260

Contextual Info: 74LS260, S260 Signetics Gates Dual 5-Input NOR Gate Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL 74LS260 9ns 4mA 74S260 4ns 22mA FUNCTION TABLE INPUTS OUTPUT A B C D E Y H X X X X L X H X X X L X X H X

7421 pin configuration

Abstract: 7420 pin configuration 74LS20 PIN CONFIGURATION 7421 logic gate 7421 AND 74LS20 function table 74LS21 PIN CONFIGURATION TTL 7420 7421 AND gate PIN CONFIGURATION 7420
Contextual Info: Signehcs I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7420 10ns 8mA 74LS20 10ns 0.8mA 8mA 74S20 3ns 7421 12ns 8mA 74LS21

74LS622

Abstract: SN74LS XS620 SN74LS620
Contextual Info: TYPES SN54LS620 THRU SN54LS623, SN74LS620 THRU SN74LS623 OCTAL BUS TRANSCEIVERS D 2537, A U G U S T 1979 - R E V IS E D DECEM BER 1983 Bidirectional Bus Transceivers in High-Density 20-Pin Packages S N 54LS 620, S N 54LS 621, S N 54LS 622 S N 5 4 L S 6 2 3 . . . J PACKA GE

74ALS

Abstract: DM54ALS244AJ DM74ALS244AN DM74ALS244ASJ DM74ALS244AWM J20A M20D 54ALS244A
Contextual Info: 244A NATIONAL SEMICOND -CLOGIO 31E D tSDILSS □ 0h ‘ìE3S ? 1 - 5^ O T National V ii Semiconductor - 07-00 DM54ALS244A/DM74ALS244A Octal TRI-STATE Bus Driver General Description Features This octal TRI-STATE bus driver is designed to provide the designer with flexibility in implementing a bus Interface with

74LS273

Contextual Info: Sjgnetìcs 74LS273, S273 Flip-Flops Octal D Flip-Flops Product Specification Logic Products FEATURES TYPE • Ideal buffer for MOS microprocessor or memory • Eight edge-triggered D flip-flops • High speed Schottky version available • Buffered common clock

ic 7493 truth table

Abstract: logic diagram of ic 7493 circuit diagram of ic 7493 LM 7493 INTERNAL DIAGRAM OF IC 7493 pin diagram of ic 7493 IC 7493 4bit Binary Counter 7493 flip-flop counter IC 7493 configuration ic 7493
Contextual Info: 7493, LS93 Signetics Counters 4-Bit Binary Ripple Counter Product Specification Logic Products DESCRIPTION The ’93 is a 4-bit, ripple-type Binary Counter. The device consists of four master-slave flip-flops internally con­ nected to provide a divide-by-two sec­