74S10 Search Results

Contextual Info: C A LIFO RN IA M IC R O DEVICES S N 74S1051 ►► ► ► ► 12-BIT SCHO TTKY BARRIER DIO DE BUS TER M IN A TO R F eatu res Applications • • • • • • 24 integrated diodes in a single package offers 12 channel, dual rail clam ping action Provides proper bus term ination independent o f

CI 7474

Abstract: CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi (3 J Q 2 — J SD 0 CP Z o (3 11 4 K Ä 0 Co “LT in > _6 12 CP 3 -0 14 K Co ° 7 o-i- CP 13 —c K Cd °

Contextual Info: TECHNICAL DATA SHEET F 75 Ω 74S101-K100 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/06.07/5.0 Connector parts Center contact Outer contact

EIA-550

Abstract: K150 74s101
Contextual Info: TECHNICAL DATA SHEET F 75 Ω 74S101-K150 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/06.07/5.0 Connector parts Center contact Outer contact

NAND Gate 3-Input 7410

Abstract: 74LS10PC
Contextual Info: 10 CO NNECTIO N DIAGRAMS PINO UT A '''54/7410 ^é4H/74H10 ^54S/74S10 ö / ' o -h? ^ 4 L S /7 4 L S 1 0 ^ / y 7 TRIPLE 3-INPUT NAND GATE ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE M ILITARY GRADE V cc = +5.0 V ±5%, T a = 0° C to +70° C

IC 7410

Abstract: 7410 JRC IC 7430 IC 7420 IC 7400 nand OF IC 7410 7410 ic ls 7400 hc 7400 7410 1c
Contextual Info: - 25- Triple 3 Input NAND 7410 Vcc 1C IV ac 38 3A 3Y ninininiLriiniriif ft IB 2A 2B 2C 2Y GND O Y = A •B •C 74S10 N LS ALS ALSK F S AS AC max L-*H T 22 15 11 8 6 4.5 4.5 11.1 12. 3,24 30 ns tpd max H—»L 1 15 15 10 7 5. 3 5 4.5 11.1 12.3 24 30 ins IN

K031

Contextual Info: TECHNICAL DATA SHEET F 75 Ω 74S101-K031 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/06.07/5.0 Connector parts Center contact Outer contact

Contextual Info: TECHNICAL DATA SHEET F 75 Ω 74S101-K100 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/12.04/3.0 Connector parts Center contact Outer contact

TTL 74ls74

Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 ui 9 D UJ -=pi (3 J Q 2 — J SD 0 CP Z o (3 4 K Ä Co “LT in > </> O a 3 -0 K Co ° I- 3 a. I- 3 O 4-0 Co ? 15 D61 54/7474, 54H/74H74,

abt16244a

Abstract: 74S1051 4kv ESD immunity
Contextual Info: SN 74S1051 CALIFORNIA MICRO DEVICES 12-BIT SCHOTTKY BARRIER DIODE BUS TERMINATOR Features • 24 integrated diodes in a single package offers 12 channel, dual rail clamping action • Provides proper bus termination independent of external line or card loading conditions

Contextual Info: CALIFO RN IA M IC R O DEVICES SN 74S1051 ►►►►► 12-BIT SCHOTTKY BARRIER DIODE BUS TERMINATOR Features Applications • • • • • • 24 integrated diodes in a single package offers 12 channel, dual rail clamping action Provides proper bus termination independent of

TTL 7411

Abstract: PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10
Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification I TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA

TTL 74ls74

Abstract: 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73 74ls74 TTL 74ls76 74LS109
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL M A S T E R /S LA V E E D G E -T R IG G E R E D D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi J Q (3 CP o K Z 2 — J SD 0 _6 Co (3 “LT in > z o Q J CP I- 3 a. 3 O So J - Ö K 4-0

K031

Contextual Info: TECHNICAL DATA SHEET F 75 Ω 74S101-K031 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/12.04/3.0 Connector parts Center contact Outer contact

CI 7410

Abstract: CI 74ls10 74LS10 74LS10 pin configuration N7410F N7410N N74H10F N74H10N N74LS10F N74LS10N
Contextual Info: PIN CONFIGURATIONS 54/7410 54H/74H10 54S/74S10 54LS/74LS10 ORDERING CODE See Section 9 for further Package and Ordering Information. Œ *14*] VCC Œ E m m m [I 2Sl Œ 3 Œ PACKAGES C O M M E R C IA L RANGES to »70"C PIN CONF. VCC - 5V * 5"/o; T a = 0°C

TTL 7410

Abstract: ua 7411 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 TTL 7411 74LS10 pin configuration 7411 pin configuration 74LS11 function table 74ls 7410 pin configuration
Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products • Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns

Contextual Info: GD54/74S10 TRIPLE 3-INPUT POSITIVE NAND GATES Description Pin Configuration This device contains three independent 2-input NAND gates. It performs the Boolean functions Y = A .B .C or Y=A+"BVC in positive logic. Vcc m 1C hi 1Y 3C 3B n^i rn h°ì 3A fi 3Y rn

Contextual Info: TECHNICAL DATA SHEET F 75 Ω 74S101-K150 AIRLINE PLUG/JACK All dimensions are in mm; tolerances according to ISO 2768 m-H Interface According to IEC 169-24 ; EIA-550 Documents N/A Material and plating RF_35/12.04/3.0 Connector parts Center contact Outer contact

LM 7410

Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns

ABT16244A

Contextual Info: CALIFO RN IA M IC R O DEVICES SN 74S1051 ►► ► ►► 12-BIT S C H O TT KY BARRIER DIODE BUS TER M IN A TO R F e a tu re s A pplications • • • • • • 2 4 in te g ra te d diodes in a single package offers 12 channel, dual rail cla m p in g a ctio n

74LS109D

Abstract: 4151 cp IR 9024 74LS109PC 74S109
Contextual Info: I 1 NATIONAL SEMICOND -CLOGIO OSE D 1 5 0 1 1 5 2 □Dt,37flS 1 | T~ ¥ 6 - 0 7 - 0 7 109 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S109 54LS/74LS109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — T he ’109 co n sists of two high speed, com pletely indepen­

Contextual Info: 74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for

74S206

Abstract: 74s201
Contextual Info: 54/74S ELECTRICAL CHARACTERISTICS See Notes - Page 50 INPUT VOLTAGE V|L (V) PARAMETER TEST CONDITIONS LOW LEVEL VÇC~MIN MIN TYP MAX OUTPUT VOLTAGE V|C(V) V|H (V) HIGH LEVEL CLAMP VOLTAGE V çç= M IN VCC = “ IN l|=-18 mA MIN TYP MAX MIN TYP VOH (V) HIGH LEVEL

74S107

Contextual Info: BiCMOS STATIC RAM 64K 8K x 8-BIT CACHE-TAG RAM IDT71B74 In te g ra te d D evice T ec hnology, In c . FEATURES: DESCRIPTION: • H igh-speed ad dress to M A TC H com parison tim e — C om m ercia l: 8/1 0/12 /15/20ns (m ax.) • H igh-speed ad dress acce ss tim e