TTL 74LS74 Search Results

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

74LS08 fan-in

Abstract: 74LS398 74LS273 74LS14 Hex Inverter definition MC74F579 74LS181 74ls795 74LS299 Decade Up/Down counter 3 State ttl buffer 74LS245
Contextual Info: Selection Information FAST/LS TTL 1 Circuit Characteristics 2 Design Considerations, Testing and Applications Assistance Form 3 FAST Data Sheets 4 LS Data Sheets 5 Reliability Data 6 Package Information Including Surface Mount 7 FAST AND LS TTL DATA CLASSIFICATION

74LS82

Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
Contextual Info: GOULD 4055916 GOULD SEMICONDUCTOR SEMICONDUCTOR DIV DIV 03E D | 03E MDSSTlb 09920 D UCICmEU T-4 3I-V 7400 TTL Cells •> GOULD CM OS Gate Array and Standard Cell Library Electronics Features General Description • Over 200 functions available. 7400 TTL Cells, a member of Gould’s EXPERT ASIC

74LS86 motorola

Abstract: 74LS86 full adder motorola 74LS86 74HG74 TTL 74ls83 74ls74 ALL 74LS74 motorola 74LS74 TTL 74ls74 MCA1200ECL
Contextual Info: LOGIC PRODUCTS — SEMICUSTOM continued Motorola Macrocell Array Families ft/i/t/t/t/t/t/à i / l / j / i / 1 / f/f /i Technology TTL ECL ECL/TTL 3-Mlcron Sllicon-Gate HCMOS 2-IMicron Sllicon-Gate HCMOS G ate E qu iva le nt 652 1192 2472 533 1280 2720 2958

74ls74a

Abstract: 751A-02
Contextual Info: SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.

74LS74A

Abstract: 751A-02
Contextual Info: SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.

74LS74A

Contextual Info: <g> MOTOROLA SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The S N 54/74LS 74A dual edge-triggered flip-flop utilizes Schottky TTL cir­ cuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also com plementary Q and Q outputs.

MN5245

Abstract: 5246M MN5245A 5246A MN5246A MN375
Contextual Info: • 850nsec Maximum Conversion Time • Guaranteed 1.1MHz Conversion Rate • 1MHz Sampling Rate When used with MN376 T/H Amplifier • Multisourced • Small 40-Pin DIP • No Missing Codes Guaranteed Over Temperature • TTL Compatible • 3-State Output Buffer

transistor cross reference

Abstract: MPT3N40 Westinghouse SCR handbook LT 8224 ZENER DIODE sje389 N9602N npn transistor RCA 467 TFK 7 segment displays PUT 2N6027 delco 466
Contextual Info: C K TBD DOLLY LIST LOGO LIST SAFETY & RELIABLTY TEK PN SYSTEM II DIGITAL IC's MEMORIES. MOS. CM OS.ECL. TTL MICROPROCESSOR SPECIAL FUNCTION IC's DIGITAL / LINEAR ARRAYS LINEAR IC'S (PURCH) TEK-MADE IC’s 3 IC's INDEX (COLORED PGS) INCL PRGMD. SCRND.ETC

Current 74HCT74

Abstract: 74ls74 ic chip 74HCT74 DATASHEET M74HCT74 74LS74 gate diagram 74HCT74 truth table 74LS74 SPECIFICATIONS pin DIAGRAM OF IC 74ls74 M54HCT74 M54HCT74F1R
Contextual Info: M54HCT74 M74HCT74 DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR . . . . . . . HIGH SPEED fMAX = 53 MHz TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE CAPABILITY

FZH115B

Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
Contextual Info: Digital I.C.s, 74INTEGRATED CIRCUITS DIGITAL TTL, 74LS & 74HC Series Quad 2-input NAND gate Quad 2-input NAND gate, open collector Quad 2-input NOR gate Quad 2-input NOR gate, open collector Hex inverter Hex inverter, O/C collector Hex inverter, Buffer 30V O/P

74LS74A

Contextual Info: M M O T O R O L A SN54/74LS74A D E S C R I P T I O N - The S N 5 4 L S /7 4 L S 7 4 A dual edge-triggered flip-flop u tilizes Schottky TTL circu itry to produce high speed D-type flip-flops. Each flip-flop has individual cfear and set inputs, arid also com plem entary

74HCT74 truth table

Abstract: 74hct74 74ls74 ic chip pin DIAGRAM OF IC 74ls74 t74c1 Current 74HCT74 M74HCT74
Contextual Info: / = 7 SCS-THOMSON Ä 7# RfflOMomiOra iOOS M54HCT74 M74HCT74 DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR • HIGHSPEED fMAX = 53 MHz TYP. AT V c c = 5 V ■ LOW POWER DISSIPATION Ice = 2 nA (MAX.) AT Ta = 25 "C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN.) V il = 0.8V (MAX)

IC 74ls74

Abstract: M74HCT74B1
Contextual Info: rz7 Ê S G S -T H O M S O N 5 * ^ â m i( g œ s M54HCT74 M 74HCT74 DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR • HIGHSPEED fMAX = 53 MHz (TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 2 |xA (MAX.) AT T a = 25 'C ■ COMPATIBLE WITH TTL OUTPUTS

TTL 74ls74

Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 ui 9 D UJ -=pi (3 J Q 2 — J SD 0 CP Z o (3 4 K Ä Co “LT in > </> O a 3 -0 K Co ° I- 3 a. I- 3 O 4-0 Co ? 15 D61 54/7474, 54H/74H74,

Contextual Info: M M O T O R O L A SN54LS74A SN54LS74A D E S C R I P T I O N - The S N 5 4 L S / 7 4 L S 7 4 A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary

CI 7474

Abstract: CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi (3 J Q 2 — J SD 0 CP Z o (3 11 4 K Ä 0 Co “LT in > _6 12 CP 3 -0 14 K Co ° 7 o-i- CP 13 —c K Cd °

7472 PIN DIAGRAM

Abstract: 74ls112 pin diagram 74LS112 TTL 74107 74LS74 7473 pin diagram 74h106 7476 CI 7473 Jk 7476
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 A 4 — J. 9— 10 So « Q — 2 J U» CP o 1— CD 0—3 ¿ So Q CP 8_ K Ä Q Co —I I_ Vcc = Pin 14 GND = Pin 7 in Ü Q UJ EDGE-TRIGGERED 9 O (9 D58 54H/74H106 D59b 54H/74H108

7472 PIN DIAGRAM

Abstract: 74574 74LS112 74LS74 7473 dual JK 7472 ttl TTL 7472 7472 ci CI 7473 pin diagram of ttl 7476
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE ui 3 Q </> “ UI 0 (9 D50 9000 D51 9001 D54 54/7470 13 2 A zz J So 0 g1 o° CP = Q. 1 H H (0 2 O O Q. EDGE-TRIGGERED ¡so J. So O « J. S d 0 —6 CP J . KC Äo Qo -n — J— K Q CD Vcc = Pin 14

TTL 74ls74

Abstract: 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73 74ls74 TTL 74ls76 74LS109
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL M A S T E R /S LA V E E D G E -T R IG G E R E D D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi J Q (3 CP o K Z 2 — J SD 0 _6 Co (3 “LT in > z o Q J CP I- 3 a. 3 O So J - Ö K 4-0

54175

Abstract: 74L02
Contextual Info: LO W -P O W ER S E R I E S 5 4 LS /74 LS S C H O T T K Y - C L A M P E D T R A N S I S T O R - T R A N S I S T O R LO G IC SCHOTTKY+ TTL MS! _ B U L L E T IN N O . D L -S 7 2 1 1 7 7 7, S E P T E M B E R 1972 FOR LOW-POWER, H IG H -PER FO R M A N C E D IG IT A L SYSTEMS

rm 02 l 25 u

Contextual Info: AA M OTOROLA SN54LS74A SN54LS74A D E S C R IP T IO N - T h e S N 5 4 L S /7 4 L S 7 4 A d u a l e d g e -trig g e re d flip -flo p u tiliz e s S c h o ttk y TTL c ir c u itry to p ro d u c e h ig h speed D -ty p e flip -flo p s . E ach flip -flo p has in d iv id u a l cle a r and s e t in p u ts , a n d also c o m p le m e n ta ry

74LS147

Abstract: 74ls147 pin diagram FUNCTIONAL APPLICATION OF 74LS148 74ls148 74LS147 equivalent motorola 74ls147 74ls748 SN54/74LS147 FAST AND LS TTL ls74
Contextual Info: SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are

74LS147

Abstract: 74LS148 74ls748 LS748 PIN 74LS147 LS148 ttl 74ls147 LS 74LS147 6200S ttl 74ls148
Contextual Info: <8 > MOTOROLA SN54/74LS147 SN54/74LS148 SN54/74LS748 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The S N 54/74LS 147 and the S N 54/74LS 148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order