TTL FAIRCHILD Search Results

GTLP16T1655

Abstract: curve
Contextual Info: Revised October 1999 Extended Characterization Data GTLP16T1655 DC Characteristics TTL Port – IOH/IOL Curve GTLP16T1655 TTL Port - IOZ/IIN Curve GTLP16T1655 TTL Port - IOFF Curve GTLP16T1655 TTL Port - IPU Curve GTLP16T1655 1999 Fairchild Semiconductor Corporation

CHARACTERIZATION

Abstract: GTLP6C816 GTLP6C816A curve
Contextual Info: Revised December 2000 Extended Characterization Data GTLP6C816A DC Characteristics TTL Port – IOL/IOH Curve GTLP6C816A TTL Port - IIN Curve GTLP6C816A TTL Port – IOZ Curve GTLP6C816A TTL Port – IOFF Curve GTLP6C816A 2000 Fairchild Semiconductor Corporation

GTLP18T612

Contextual Info: Revised December 2000 Extended Characterization Data GTLP18T612 DC Characteristics TTL Port – IOZ/IIN Curve GTLP18T612 TTL Port – IOFF Curve GTLP18T612 TTL Port – IPU Curve GTLP18T612 GTLP Port – IOL Curve GTLP18T612 2000 Fairchild Semiconductor Corporation

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

Contextual Info: FAIRCHILD INTERFACE LEVEL TRANSLATORS Power Dissipation mW Logic/Connection Diagram s +12 to +20 0.0 (+VJ-2.0 +0.4 90 440 G12 6A Dual ECL-TTL +5.0 -5.2 +2.4 +0.4 6.0 375 E15 6B TTL-MOS +5.0 0.0 to -30 Vtap -1-0 <-V)+2.0 z o > UJ Û 1 9112 TTL-H LD TL Hex

7SEG COM ANODE

Abstract: 7-seg 7-seg ANODE COMMON 7seg D143 TTL 74LS48 TTL 7446 decoder 74LS48 7448 decoder decoder 74LS47
Contextual Info: FAIRCHILD INTERFACE DISPLAY DRIVERS Cont'd 5.5 H — 125 D141 4L.6B, 9B 2 5449 7-Seg Decoder TTL Yes Yes No 9.6 5.5 H — 165 D142 3I 3 54LS/ 74LS49 7-Seg Decoder/ TTL Dvr OC Yes Yes No 1.3 5.5 H — 40 D142 3I.6A, 9A 4 9302 1-of-10 OC Dvr TTL Yes No Yes

decoder 7448

Abstract: BCD D147 D142 7448 decoder mos 9368 decoder 74LS47 7-seg 9317C ttl 74ls48 9317B
Contextual Info: FAIRCHILD INTERFACE DISPLAY DRIVERS Yes Yes No 1.3 5.5 H — 125 D141 4L,6B, 9B 2 5449 7-Seg Decoder TTL Yes Yes No 9.6 5.5 H — 165 D142 3I 3 54LS/ 74LS49 7-Seg Decoder/ TTL Dvr OC Yes Yes No 1.3 5.5 H — 40 D142 3I,6A, 9A 4 9302 1-of-10 OC Dvr TTL Yes

2n2222 fairchild

Abstract: 74OL60XX
Contextual Info: 74OL6000, 74OL6001, 74OL6010, 74OL6011 Optoplanar High-Speed Logic-to-Logic Optocouplers LSTTL to TTL Buffer TTL Inverter CMOS Buffer CMOS Inverter Description 74OL6000 74OL6001 74OL6010 74OL6011 Features • Industry first LSTTL to TTL and LSTTL to CMOS

Contextual Info: * SYNERGY LOW-POWER HEX TTL-TO-PECL TRANSLATOR SY100S391 SEMICONDUCTOR DESCRIPTION FEATURES Operates from a single +5V supply Differential PECL outputs The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique

DTL or TTL integrated logic circuits

Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75450APC

Abstract: 9109 DC fairchild ECL 75450a
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 . 0 0.4 90 440 TO-86 6A.9A 9 5 9 5 * Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver

75452ATC

Abstract: 75452A
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

754538

Abstract: 9109 DC 55450B 75450BDC
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

mw 137

Abstract: fairchild ECL
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

55450B

Abstract: 75451B
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

74 TTL PACKAGE OUTLINES

Abstract: 75451ATC 1606B 55451A 75451ARC
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75450apc

Abstract: 10125 ecl to ttl fairchild 9112 7S45 pin diagram for all 74 series ttl gates
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 . 0 0.4 90 440 TO-86 6A.9A 9 5 9 5 * Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver

75451

Abstract: 55450B 75452B fairchild 9112
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75452

Abstract: 55450B
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

fairchild ECL

Abstract: 75453btc 55450B 754S3B
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

GTLP8T306

Abstract: MTC24
Contextual Info: March 1998 GTLP8T306 8-Bit TTL-to-GTLP Bus Transceivers Preliminary General Description Features The GTLP8T306 is an 8-bit bus transceiver that provides TTL to GTLP signal level translation. The device provides a high speed interface between cards operating at TTL logic

Contextual Info: 100325 100325 Low Power Hex ECL-to-TTL Translator Literature Number: SNOS129A 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit

100324

Contextual Info: Revised November 1999 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable

100324PC

Abstract: 100324QC 100324QI 100324SC M24B MS-013 N24E V28A 100124 100324
Contextual Info: Revised August 2000 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable