74LS49 Search Results

Contextual Info: • BCD-tO’Seven Segment Decoder/Driver with Open collector outputs IP IN ARRANGEMENT The H D 74LS49 features active-high outputs for driving lamp buffer. This circuit incorporates d direct blanking input. Segment identification and resultant displays are shown below.

Contextual Info: M MOTOROLA SN54/74LS490 DUAL DECADE COUNTER The S N 54/74LS 490 contains a pair of high-speed 4-stage ripple counters. Each half of the S N 54/74LS 490 has individual Clock, Master Reset and Mas­ ter Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code.

74ls491

Contextual Info: July 1989 DM54LS491/74LS491 10-Bit Counter General Description Features/Benefits The ten-bit counter can count up, count down, set, and load 2 LSB’s, 2 MSB’s and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET overrides LOAD, COUNT and HOLD. LOAD overrides COUNT.

Contextual Info: LS TTL DN74LS Series 74LS490 KH4U4qo 74LS490 Dual 4 -bit Decade Counters • D escrip tio n DN 74LS490 contains two asynchronous decade counter circuits with direct coupled reset input and nine direct-coupled set inputs. P -2 ■ Features • Two circuits corresponding to LS90 and L S290 for high

DM74LS491N

Contextual Info: LS491 S National Semiconductor DM54LS491/74LS491 10-Bit Counter General Description Features/Benefits The ten-bit counter can count up, count down, set, and load 2 LSB’s, 2 MSB’s and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET over­

74ls490

Contextual Info: 74LS490 Signetics Counter Dual BCD Decade Ripple Counter Product Specification Logic Products FEATURES TYPE • T w o B C D d e c a d e c o u n te rs • A s y n c h ro n o u s M a s te r S e t s e t-to -9 • A s y n c h ro n o u s M a s te r R e s e t

truth table NOT gate 74

Abstract: 74LS490 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS490 DUAL DECADE COUNTER The SN54 / 74LS490 contains a pair of high-speed 4-stage ripple counters. Each half of the SN54 / 74LS490 has individual Clock, Master Reset and Master Set Preset 9 inputs. Each section counts in the 8, 4, 2, 1 BCD code.

Contextual Info: 74LS490 Signetics Counter Dual BCD Decade Ripple Counter Product Specification Logic Products FEATURES • Two BCD decade counters • Asynchronous Master Set set-to-9 • Asynchronous Master Reset (clear) TYPE 74LS490 The '490 is a Dual BCD Decade Ripple

74ls491

Abstract: 200II
Contextual Info: LS491 531 National JuM Semiconductor DM54LS491/74LS491 10-Bit Counter General Description Features/Benefits The ten-bit counter can count up, count down, set, and load 2 LSB's, 2 MSB’s and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET over­

74ls490

Contextual Info: MOTOROLA SN54/74LS490 DUAL DECADE COUNTER The SN54/74LS490 contains a pair of high-speed 4-stage ripple counters. Each half of the SN54/74LS490 has individual Clock, Master Reset and Mas­ ter Set Preset 9 inputs. Each section counts in the 8, 4, 2, 1 BCD code.

02D7

Contextual Info: O T National æ æ Semiconductor DM54LS491/74LS491 10-Bit Counter General Description Features/Benefits The ten-bit counter can count up, count down, set, and load 2 LSB's, 2 MSB’s and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET over­

74ls491

Abstract: 74ls491 timing diagram DM74LS491N 8332 prom C1995 DM54LS491 DM54LS491J DM74LS491J J24F N24C
Contextual Info: DM54LS491 74LS491 10-Bit Counter General Description Features Benefits The ten-bit counter can count up count down set and load 2 LSB’s 2 MSB’s and 6 middle bits high or low as a group All operations are synchronous with the clock SET overrides LOAD COUNT and HOLD LOAD overrides COUNT

7SEG COM ANODE

Abstract: 7-seg 7-seg ANODE COMMON 7seg D143 TTL 74LS48 TTL 7446 decoder 74LS48 7448 decoder decoder 74LS47
Contextual Info: FAIRCHILD INTERFACE DISPLAY DRIVERS Cont'd 5.5 H — 125 D141 4L.6B, 9B 2 5449 7-Seg Decoder TTL Yes Yes No 9.6 5.5 H — 165 D142 3I 3 54LS/ 74LS49 7-Seg Decoder/ TTL Dvr OC Yes Yes No 1.3 5.5 H — 40 D142 3I.6A, 9A 4 9302 1-of-10 OC Dvr TTL Yes No Yes

Contextual Info: 74LS490 Signetics Counter Dual BCD Decade Ripple Counter Product Specification Logic Products FEATURES TYPE 74LS490 PACKAGES CPb HI M Rb Ü ] »O b ° i. E Ï 3 M Sb °2 l Œ HI °1 b °3 * ¡T ID °2 b 3 °3 b [_4_ QND [ T INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

74LS490

Abstract: 198S 1N3064 1N916 74LS ISM040S N74LS490N bcd counter 74 90 pin diagram of 74LS
Contextual Info: 74LS490 Counter Signetics Dual BCD Decade Ripple C ounter Product Specification Lo gic Products FEATURES • Tw o BCD decade counters • Asynchronous Master Set set-to-9 • Asynchronous Master Reset (clear) (T |T 53 vcc MR, o to m 53 MRb 53 Qob ZU MSb

bcd decade counter ttl

Abstract: FAST AND LS TTL truth table NOT gate 74 74LS490 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS490 DUAL DECADE COUNTER The SN54 / 74LS490 contains a pair of high-speed 4-stage ripple counters. Each half of the SN54 / 74LS490 has individual Clock, Master Reset and Master Set Preset 9 inputs. Each section counts in the 8, 4, 2, 1 BCD code.

IC 7449

Abstract: 7449 7-segment decoder logic diagram 7449 BCD to 7-segment pin DIAGRAM OF IC 74
Contextual Info: NATIONA L SEUICOND -CLOGIO D5E D | LS011BE D0t3böS fi ^ ~ V 49 CO NNECTIO N DIAGRAM PINO UT A 54/7449 54LS/74LS49 1— r T4 ] Vcc Ai [ T a BCD TO 7-SEGMENT DECODER 2£ [ Taj * b ï[T n ia A ,E ïT ]a Ao [ T To] b « [T 3 « GND [ 7 DESCRIPTION — The ’49 translates fo u r lines of BCD 18421 in put data in to

Signetics 565

Abstract: 1N3064 1N916 74LS 74LS490 N74LS490N
Contextual Info: Signetics 74LS490 Counter Dual BCD Decade Ripple Counter Product Specification Logic Products FEATURES • Two BCD decade counters • Asynchronous Master Set set-to-9 • Asynchronous Master Reset (clear) TY PE T Y P IC A L f MAx TY P IC A L SU P P LY C U R R E N T

decoder 7448

Abstract: BCD D147 D142 7448 decoder mos 9368 decoder 74LS47 7-seg 9317C ttl 74ls48 9317B
Contextual Info: FAIRCHILD INTERFACE DISPLAY DRIVERS Yes Yes No 1.3 5.5 H — 125 D141 4L,6B, 9B 2 5449 7-Seg Decoder TTL Yes Yes No 9.6 5.5 H — 165 D142 3I 3 54LS/ 74LS49 7-Seg Decoder/ TTL Dvr OC Yes Yes No 1.3 5.5 H — 40 D142 3I,6A, 9A 4 9302 1-of-10 OC Dvr TTL Yes

IC 74LS90

Contextual Info: 490 !-/ 5 /C o 5 7 C O N N E C T IO N D IA G R A M P IN O U T A 54LS/74LS490 1— r DUAL DECADE COUNTER C P a [7 T èi Vcc M R a |T T S lc P b Q 0 a [? D E S C R IP T IO N — T h e ’490 c o n ta in s a p a ir o f h ig h speed 4 -sta g e rip p le c o u n te rs . Each h a lf o f th e '490 has in d iv id u a l C lo c k , M aster Reset and

DN74LS490

Abstract: LS290 LS90
Contextual Info: LS TTL DN74LS Series D N 74LS490 74LS490 ^ 74 ts 4q o Dual 4 - b it Decade Counters • Description P -2 D N 74LS490 contains tw o asynchronous decade counter circuits w ith direct coupled reset input an d nine direct-coupled set inputs. ■ Features •

sn74ls498

Abstract: SN54LS498 74LS498
Contextual Info: 8 -B it S hift Register SN54/74LS498 Features/Benefits Ordering Information • 8-blt shitl register for serial-to-paratlel and paraliel-toserial applications PART NUMBER PACKAGE • 8 bits match byte boundaries SN54LS498 JS, F • Bus-structured pinout 74LS498

Contextual Info: Signetics 74LS490 Counter Dual BCD Decade Ripple Counter Product Specification Logic Products FEATURES PIN CONFIGURATION CP . [ T Ï3 VCC MR, [2_ H CP„ °o. Œ 3 3 MRb MS, [4_ 1 ] 0» T HI °1b QND ORDERING CODE COMMERCIAL RANGE VCC = 5V ±5% ; Ta = 0°C to + 70°C

Contextual Info: SN54LS490, 74LS490 DUAL 4-BIT DECADE COUNTERS OCTOBER 1 9 7 6 - REVISED M AR C H 1 9 8 8 S N 5 4 L S 4 9 0 . . . J OR W P AC K A G E S N 7 4 L S 4 9 0 . . . D . J O R N PAC KA G E Dual Versions of Popular SN54LS90 and SN74LS90 Counters TO P V IE W Dual Counters Can Significantly Improve