TXC03102 Search Results

22-bit

Contextual Info: S A R A II Segmentation and Reassembly Device TXC-05551 DATA SH EE T PRODUCT PREVIEW FEATURES DESCRIPTION • Full duplex segmentation and reassembly ot multiple VCs up to 155 Mbit/s in each direction • Integrated SONET/SDH 155.52 Mbit/s framer. • Optional 8-bit UTOPIA interface

GR-253-CORE

Abstract: GR-499-CORE MT8980 ROB-1998 e1 E2 e3 liu transceiver NPRM
Contextual Info: T1Fx8 Device 8-Channel T1 Framer TXC-03108 TECHNICAL OVERVIEW FEATURES DESCRIPTION • D4 SF, ESF including HDLC Link support , auto search, and independent transparent framing modes • Encodes/decodes AMI/B8ZS and forced ones density line codes • Fractional T1; Gapped clock or marker; Auxiliary

Contextual Info: tmän S w it c h „ DS1MX7 Device DS1 Mapper 7-Channel TXC-04201B x- DATA SHEET DESCRIPTION FEATURES • Seven independent 1.544 Mbit/s DS1 mappers • Single byte-parallel Telecom Bus @ 6.48 MHz 28 Slots or 19.44 MHz (84 Slots) • Floating V T1.5 Byte Synchronous mapping for

TG29

Abstract: TG29-1205 ps4 schematic ps3 schematic AN068 LXT360 LXT360QE TG29-1205NX TXC-031043
Contextual Info: Universal Four-Port Network Interface T1/E1 Long-Haul/ShortHaul Design Kit Application Note January 2001 Order Number: 249169-001 As of January 15, 2001, this document replaces the Level One document known as AN068. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

ALI-25

Abstract: ALI-25C SALI-25C ETHERMAP-3 PT, ED. B, 1A 05802
Contextual Info: CUBIT-Pro Device CellBusTM Bus Switch TXC-05802 DATA SHEET DESCRIPTION FEATURES • UTOPIA and 16-Bit ATM or PHY Layer cell interfaces • Inlet-side address translation and routing header insertion, using external SRAM of up to 256 kB • Programmable OAM-cell and RM-cell routing

TRA12

Contextual Info: BACK CUBIT-Pro Device CellBusTM Bus Switch TXC-05802 DATA SHEET DESCRIPTION FEATURES • UTOPIA and 16-Bit ATM or PHY or ALI-25 PHY Layer cell interfaces • Inlet-side address translation and routing header insertion, using external SRAM of up to 256 kB

SDH siemens

Abstract: ALCATEL PABX projects based on mobile communication and networking Alcatel optical transceiver STM 1
Contextual Info: Silicon Solutions Integrating Communications Worldwide communicator From the President T he vision of the current administration for the information superhighway is to "create a doorto-door, high-performance information network to link every home, business, laboratory, classroom, and

multiplexing demultiplexing e2 e3

Abstract: ALI-25 STM-16 Design Seminar Signal Transmission
Contextual Info: R TS-501 TECHNOLOGY SEMINAR Technology Seminar • Voice Networks Telephony • Data Networks (Datacom) This is the Voice Annotated Edition of the TranSwitch Technology Seminar. When viewing this document on a Windows or Macintosh platform, click on the Win/Mac Sound logos to hear the voice annotation.

TXC-02050

Abstract: 8-34-Mbit
Contextual Info: TranSwitch VLSI: Powering Communication Innovation communicator From the President I n the era of worldwide competition, the endusers as well as the network providers want the flexibility and versatility to respond quickly to the changing environment. According to A. S.

ALI-25

Abstract: multiplexing demultiplexing e2 e3 multiplexing e2 frame e3 strand demultiplexer standar LTE TS-501
Contextual Info: R TS-501 TECHNOLOGY SEMINAR Technology Seminar • Voice Networks Telephony • Data Networks (Datacom) Copyright c 1996 TranSwitch Corporation ALI-25, COBRA, CUBIT, CellBus and PHAME are trademarks of TranSwitch Corporation TranSwitch, TXC, SONGEN, XBERT, and SARA are registered trademarks of TranSwitch Corporation

7 pin ic cp43

Abstract: ALI-25 ALI-25C rh30100
Contextual Info: CUBIT-Pro Device t r a n S w it c h CellBus Bus Switch TXC-05802 X- DATA SHEET DESCRIPTION FEATURES • UTOPIA and 16-Bit ATM or PHY or ALI-25 PHY Layer cell interfaces • Inlet-side address translation and routing header insertion, using external SRAM of up to 256 kB

TG29-1205NX

Abstract: LXT360QE LEVEL ONE COMMUNICATIONS LXT360 TG29-1205 TG74-1205N1
Contextual Info: APPLICATION NOTE 68 NOVEMBER 1997 Revision 1.0 Universal Four-Port Network Interface T1/E1 Long-Haul/Short-Haul Design Kit Introduction Universal Interface Design Kit This network interface design kit provides design guidelines for a universal long-haul and short-haul quad T1/E1

nortel CS 1500

Abstract: 1F42 QMV1025BS5 nortel cs 2000 93-001R2 1D08 QMV1025CS5 SLC96 NORTEL CPC 7415 4 -bit
Contextual Info: Lunar Data Book Publication Number: 84001.08/03-00 Issue 2 This data book applies to Lunar devices identified with the following product codes: PEC Code QMV1025BS5 CPC Code AO791373 PEC Code QMV1025CS5 (CPC Code AO799545) PROPRIETARY INFORMATION The information contained in this document is the property of Nortel Networks.

00a3r

Abstract: NORTEL CPC 1F42 motorola bipolar transistor databook st linear databook cmos logic databook ds2-s motorola cmos databook ttl databook PM4344
Contextual Info: Lunar Databook Publication Number: 84001.08/03-99 This data book applies to Lunar devices identified with the QMV1025AS5 Product Engineering Code CPC Code AO732780 PROPRIETARY INFORMATION The information contained in this document is the property of Northern Telecom. Except as

rneg2

Contextual Info: QT1F-Plus Device Quad T1 Framer-Plus TXC-03103C DESCRIPTION • D4 SF, ESF including HDLC Link support , and transparent framing modes • Encodes/decodes AMI/B8ZS and forced ones density line codes • Fractional T1 gapped clock • Monitor function for frame pulse, clock and data

Contextual Info: tm ä nx-S w it c h S FEATURES DESCRIPTION • UTOPIA and 16-Bit ATM or PHY Layer cell in­ terfaces • Inlet-side address translation and routing header insertion, using external SRAM of up to 256 kB • Programmable OAM-cell and RM-cell routing

Contextual Info: CUBIT-Pro Device CellBus Bus Switch TXC-05802 DATA SHEET PRODUCT PREVIEW FEATURES DESCRIPTION • UTOPIA and 16-Bit ATM or PHY or ALI-25 PHY Layer cell interfaces • Inlet-side address translation and routing header insertion, using external SRAM of up to 256 kB

Contextual Info: tm ä nx-S w it c h CUBIT-Pro Device CellBus Bus Switch S TXC-05802B DATA SHEET DESCRIPTION FEATURES • UTOPIA and 16-Bit ATM or PHY Layer cell in­ terfaces • Inlet-side address translation and routing header insertion, using external SRAM of up to 256 kB

Contextual Info: • TRAN ^ k 1004152 0007020 104 ■ CUBIT Device «g*, »* jiüüM R. > ,.M V. CellBus Bus Switch TXC-05801 DATA SHEET DESCRIPTION FEATURES CUBIT is a single-chip solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus bus architecture. Such systems

HP 3D6

Abstract: GR-499-CORE 23D8 CH3401
Contextual Info: QT1F-Plus Device Quad T1 Framer-Plus TXC-03103 DATA SHEET FEATURES DESCRIPTION • D4 SF, ESF including HDLC Link support , and transparent framing modes • Encodes/decodes AMI/B8ZS and forced ones density line codes • Fractional T1 Gapped Clock • Monitor function for frame pulse

Contextual Info: tm ä nx-S w it c h CUBIT-Pro Device S C ellB us Bus Switch TXC-05802B DATA SHEET DESCRIPTION • UTOPIA and 16-Bit ATM or PHY Layer cell in­ terfaces • Inlet-side address translation and routing header insertion, using external SRAM of up to 256 kB

TAB 429 H

Abstract: ch3406
Contextual Info: QT1F-Plus Device t r a n S w it c h QuadTI Framer-Plus TXC-03103 DATASHEET FEATURES DESCRIPTION • D4 SF; ESF including HDLC Link support , and transparent framing modes • Encodes/decodes AM I/B8ZS and forced ones density line codes • Fractional T1 Gapped Clock

c8c1

Contextual Info: Im •■ § QT1F-P/us Device l/lf l T r T H ■ Quad T1 Framer-P/i/s TXC-03103 DATASHEET FEATURES DESCRIPTION • D4 SF; ESF (including HDLC Link support), and transparent framing modes • Delects, counts and forces line code errors (BPVs and excess zeros), CFC errors (ESF only), and frame bit

Contextual Info: C O B R A Devi ce C o n s ta n t Bit Rate ATM Adaptation Layer 1 TXC-05427B DATA SHEET FEATURES DESCRIPTION COBRA COnstant Bit Rate ATM Adaptation Layer 1 is a four-channel VLSI device that implements all of the functions needed for circuit emulation over ATM. Both