UPSET Search Results

4x3 matrix keypad

Abstract: 3x4 KEYPAD matrix keypad 4x3 code assembly of matrix keypad 4x3 KEYPAD 4X3 16 4x4 Buttons Keypad Matrix 4x3 standard keypad KEYPAD 4X3 SWITCH 3x4 keyboard keypad 4x4 assembly code
Contextual Info: Standard Keypads SERIES 84 Unsealed, .750" Centers FEATURES • 3/4" Button Centers • Post Mounted • Mounts by Grooveless Retaining Rings or Heat Upset Post • Snap-Dome Contact Provides Positive Feedback Keyboards and Keypads DIMENSIONS In inches and millimeters

CDFP4-F16

Abstract: HCTS193DMSR HCTS193HMSR HCTS193KMSR HCTS193MS
Contextual Info: HCTS193MS Radiation Hardened Synchronous 4-Bit Up/Down Counter September 1995 Features • • • • • • • • • • • • • Pinouts 3 Micron Radiation Hardened CMOS SOS Total Dose 200K RAD Si SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ)

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Abstract: HCS32D HCS32DMSR HCS32HMSR HCS32K HCS32KMSR HCS32MS
Contextual Info: HCS32MS Radiation Hardened Quad 2-Input OR Gate September 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T14 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCS109MS

Abstract: CDFP4-F16 HCS109DMSR HCS109HMSR HCS109KMSR HCS109
Contextual Info: HCS109MS Radiation Hardened Dual JK Flip Flop September 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

15KV

Contextual Info: LITE-ON SEMICONDUCTOR ESD PROTECTION DIODE L15ESD12VE2 STAND-OFF VOLTAGE - 12 Volts POWER DISSIPATION - 150 WATTS GENERAL DESCRIPTION SOD-882 The L15ESD12VE2 is designed to protect sensitive semiconductor components from damage or upset due to Electro Static Discharge

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Abstract: ACTS373DMSR ACTS373HMSR ACTS373KMSR ACTS373MS
Contextual Info: ACTS373MS Radiation Hardened Octal Transparent Latch, Three-State April 1995 Features Pinouts 20 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose 300K RAD Si • Single Event Upset (SEU) Immunity

HCS00HMSR

Abstract: HCS00D HCS00DMSR HCS00K HCS00KMSR HCS00MS
Contextual Info: HCS00MS Radiation Hardened Quad 2-Input NAND Gate August 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T14 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCS273KMSR

Abstract: HCS273 HCS273DMSR HCS273HMSR HCS273MS
Contextual Info: HCS273MS Radiation Hardened Octal D Flip-Flop September 1995 Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T20, LEAD FINISH C TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCTS20D

Abstract: HCTS20DMSR HCTS20HMSR HCTS20K HCTS20KMSR HCTS20MS
Contextual Info: HCTS20MS TM Radiation Hardened Dual 4-Input NAND Gate September 1995 Features • • • • • • • • • • • • Pinouts 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD Si SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day

CDFP4-F16

Abstract: HCTS161ADMSR HCTS161AHMSR HCTS161AKMSR HCTS161AMS
Contextual Info: HCTS161AMS Radiation Hardened Synchronous Counter September 1995 Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW • Total Dose 200K RAD (Si) • Minimum LET for SEU Upsets: >100 MEV-cm2/mg

Contextual Info: LITE-ON SEMICONDUCTOR L15ESD12VE2 STAND-OFF VOLTAGE - 12 Volts POWER DISSIPATION - 150 WATTS ESD PROTECTION DIODE GENERAL DESCRIPTION SOD-882 The L15ESD12VE2 is designed to protect sensitive semiconductor components from damage or upset due to Electro Static Discharge

Contextual Info: L18ESD12VA2 LITE-ON SEMICONDUCTOR STAND-OFF VOLTAGE - 12 Volts POWER DISSIPATION - 180 WATTS ESD PROTECTION DEVICE GENERAL DESCRIPTION SOD523 The L18ESD12VA2 is designed to protect sensitive semiconductor components from damage or upset due to Electro Static Discharge ESD .

L15ESD12VE2

Abstract: L15ESD
Contextual Info: LITE-ON SEMICONDUCTOR ESD PROTECTION DIODE L15ESDxVE2 STAND-OFF VOLTAGE - 12~24 Volts POWER DISSIPATION - 150 WATTS GENERAL DESCRIPTION SOD-882 The L15ESDxVE2 is designed to protect sensitive semiconductor components from damage or upset due to Electro Static Discharge

Contextual Info: 9 SEU Mitigation for Stratix V Devices 2013.05.06 SV51011 Subscribe Feedback This chapter describes the error detection features in Stratix V devices. You can use these features to mitigate single event upset SEU or soft errors. Related Information Stratix V Device Handbook: Known Issues

Contextual Info: U HS-26C31RH S E M I C O N D U C T O R Radiation Hardened Quad Differential Line Driver November 1995 Features Pinouts • 1 . 2 Micron Radiation Hardened CMOS - Total Dose Up to 300K RAD Si) - Dose Rate Upset > 1x109 RAD/Sec (20ns Pulse) • Latchup Free

Contextual Info: HS-82C54RH S E M I C O N D U C T O R Radiation Hardened CMOS Programmable Interval Timer August 1995 Features Pinouts • Radiation Hardened - Total Dose >105 RAD Si - Transient Upset > 108 RAD (Si)/sec - Latch Up Free EPI-CMOS - Functional After Total Dose 1 x 106 RAD (Si)

krad

Abstract: 67025E TM1019 RAM SEU
Contextual Info: DPR SCMOS2 Technology Dual Port RAM 8K16 Tolerance to Radiation Abstract This paper proposes a review of the data gathered during radiation testing for the 8Kx16 dual port RAM manufactured using the Radiation Tolerant version of the 0.6µm SCMOS2/2 technology. Both Upset sensitivity

SCS750

Abstract: bc 7-25 Programmable Logic Controller radiation SCS750F 1000X 750FX ppc 750fx IBM PowerPC Processor 350 Mips IBM 750FX powerpc dhrystone PowerPC 750FX
Contextual Info: SCS750 SCS750 SUPER COMPUTER FOR SPACE TM Super Computer for Space SCS750F® FLIGHT MODULE Overview of Specifications • One board upset every 100 years in a GEO or LEO Orbit • Up to 1000X Better Performance Than Current Space Processor Boards • Highest Space-Qualified Performance @1800 MIPS

Contextual Info: Æ ic te - m ! v 2 .0 Radiation-Hardened Field Programmable Gate Arrays Features Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Im m unity Guaranteed QML Qualified Devices

HCTS30

Abstract: HCTS30DMSR HCTS30HMSR HCTS30KMSR HCTS30MS
Contextual Info: HCTS30MS Radiation Hardened 8-Input NAND Gate August 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T14 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCTS574DMSR

Abstract: HCTS574HMSR HCTS574KMSR HCTS574MS
Contextual Info: HCTS574MS August 1995 Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered Features • • • • • • • • • • • • • Pinouts 3 Micron Radiation Hardened CMOS SOS Total Dose 200K RAD Si SEP Effective LET No Upsets: >100 MEV-cm2/mg

Contextual Info: HS- 82 C 54 RH S ttftsras Radiation Hardened CMOS Programmable Interval Timer August 1995 Features Pinouts • Radiation Hardened 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T24 TOP VIEW - Total Dose > 1 0 5 RAD (Si) - Transient Upset > 10 RAD (Si)/sec

HR2340

Abstract: sram pull down honeywell memory sram
Contextual Info: b3E D • MSS1Ö7E 0DD1D3L, EIT ■ H 0 N 3 H O ilG y W G lI HONEYÙJELL/S S E C Preliminary RICMOS SEA OF TRANSISTORS GATE ARRAY HR2340 FEATURES RADIATION HARDNESS • Total Dose Hardness of >1x106 rad Sl02 • Dose Rate Upset Hardness > 1x103rad(Si)/sec

MSI Logic

Abstract: Structure of D flip-flop UNITED TECHNOLOGIES MICROELECTRONICS CENTER "radhard" overview Upset
Contextual Info: Single Event Upset Design Techniques for UTMC’s RadHard MSI Logic Family Overview A Single Event Upset SEU is the result of an ion transitioning through a semiconductor structure and depositing charge on a critical circuit node within that structure. In a CMOS logic circuit,