UR5595 Search Results
UR5595 Datasheets (4)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| UR5595 | Unisonic Technologies | DDR TERMINATION REGULATOR | Original | 315.16KB | 12 | ||
| UR5595-S08-R | Unisonic Technologies | DDR TERMINATION REGULATOR | Original | 315.16KB | 12 | ||
| UR5595-S08-T | Unisonic Technologies | DDR TERMINATION REGULATOR | Original | 315.16KB | 12 | ||
| UR5595-SH2-R | Unisonic Technologies | DDR TERMINATION REGULATOR | Original | 315.15KB | 12 |
UR5595 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
UR5595L
Abstract: UR5595 UR5595L-SH2-R UR5595-S08-R UR5595-S08-T UR5595-SH2-R
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Original |
UR5595 UR5595 QW-R502-062 UR5595L UR5595L-SH2-R UR5595-S08-R UR5595-S08-T UR5595-SH2-R | |
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Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM. |
Original |
UR5595 UR5595 QW-R502-062 | |
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Contextual Info: UNISONICTECHNOLOGIESCO., LTD UR5595 CMOS IC DDR T ERM I N AT I ON REGU LAT OR ̈ DESCRI PT I ON The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM. |
Original |
UR5595 UR5595 QW-R502-062 | |
UR5595L
Abstract: UR5595L-SH2-R UR5595 UR5595-S08-R UR5595-SH2-R
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Original |
UR5595 UR5595 QW-R502-062 UR5595L UR5595L-SH2-R UR5595-S08-R UR5595-SH2-R | |
UR5595LContextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM. |
Original |
UR5595 UR5595 QW-R502-062 UR5595L | |
UR5595Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM. The device |
Original |
UR5595 UR5595 QW-R502-062 |