VIAL Search Results

Contextual Info: Standard Products UT4090 RadHard FPGA Advanced Data Sheet February 21, 2001 FEATURES q 0.35µm four-layer metal non-volatile CMOS process for smallest die sizes q One-time programmable, ViaLink TM antifuse technology for personalization q 150 MHz 16-bit counters, 200 MHz datapaths, 80+ MHz

16X24B

Abstract: CF160 PF100 PF144 PL84 CPGA Package Diagram
Contextual Info: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

PL84

Abstract: ql16x24bl PF100 PF144
Contextual Info: QL16x24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and

QL4090

Abstract: pASIC 1 Family 160CQFP 208-CQFP
Contextual Info: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

PF144

Abstract: PQ208 QL24X32B-1PQ208C
Contextual Info: QL24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS …8,000 usable ASIC gates, 180 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

QL8X12B

Abstract: PF100 pASIC 1 Family circuit diagram of Tri-State Buffer using CMOS
Contextual Info: QL8X12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. …1,000 usable ASIC gates,

transistor 1f sot-23

Abstract: sot23 AJ motorola sot 23 marking transistor marking code SOT-23 BC817B marking 1F transistor sot-23 transistor marking code SOT-23 2F marking 1P sot-23 sot 23 transistor 2f sot transistor pinout
Contextual Info: oatrif ©® SOT 23 Microminiature Space Saving Alternatives for Discrete Devices • Packaging — M otorola standard shipping A wide variety of discrete components from method for SOT’s is in vials; additionally, in M otorola's repertoire of reliability-proven sem icon­

Contextual Info: Q L 8X 12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. . 1,000 usable ASIC gates,

PQFP208

Abstract: CCGA 484 socket CLGA484 PBGA280 PBGA484 5962-0422 SDRAM edac transistor smd qe UT6325 RAM EDAC SEU
Contextual Info: Aeroflex Colorado Springs RadHard Eclipse FPGA Frequently Asked Questions NOTE - FAQs WILL BE UPDATED ON A REGULAR BASIS Introduction: QuickLogic has licensed their metal-to-metal VialinkTM technology to Aeroflex Colorado Springs (Aeroflex). The agreement calls for Aeroflex to have access to QuickLogic’s

piher spain potentiometer

Abstract: piher spain Piher International
Contextual Info: v01 Navarra de Componentes Electrónicos, S.A. NACESA Factory & Headquarters Polígono Industrial Municipal Vial T2, Nº 22 31500 Tudela Spain Tel: +34-948-820450 Fax: +34-948-824050 Email: sales@piher.net PIHER INTERNATIONAL LTD Unit 20 Ash Kembrey Park Swindon

tms320cXX

Abstract: TMS57002 tms320c26 dsk TMS320C26 TMS320C31 TMS DASP 93C26 h004 ti31 CS4248
Contextual Info: S.E.E.D. Mr. M. Marani Viale Roma 88/A 54100 Massa MS Italy (+39) 585 792990 Fax: (+39) 585 792989 e-mail: mc4453@mclink.it Company Background S.E.E.D. is an association of electronic engineers and computer science specialists, founded in 1993 and based in Massa, Italy. S.E.E.D. operates in the DSP field giving consulting about specific applications of the customers and is able to design or integrate

seed

Contextual Info: S.E.E.D. Mr. M. Marani Viale Roma 88/A 54100 Massa Italy +39 335 372256 e-mail: mc4453@mclink.it Company Background S.E.E.D. is an association of Electronic Engineers and Computer Science Specialists, born in 1993 and based in Massa, Italy. S.E.E.D. operates in DSP field giving consulting

1000L

Abstract: PF100 QL8X12Bl
Contextual Info: QL8x12BL Wild Cat 1000L Low Power 3.3 Volt Operation, 1K Gate FPGA 2 High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5V Tolerant I/Os – Support interface to 5 Volt CMOS, NMOS and

QL24X32B-1PQ208C

Abstract: PF144 PQ208
Contextual Info: QL24x32B Wild Cat 8000 Very-High-Speed 8K 24K Gate CMOS FPGA 2 .8000 usable gates, 180 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

QuickLogic ql16x24b-1pl84c

Abstract: QL16X24B PF144 cmos io QL16X24BH TQFP 144 PACKAGE CF160 PF100 PL84
Contextual Info: QL16x24B/QL16x24BH Wild Cat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA Rev B .4000 usable gates, 122 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.

Contextual Info: QL24x32BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and

Contextual Info: QL8x12 pASIC 1 FAMILY Very-High-Speed IK 3K Gate CMOS FPGA pASIC HIGHLIGHTS Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 100 MHz, and logic cell delays of under 4 ns. High Usable Density - An 8-by-12 array of 96 logic cells provides

Contextual Info:    VIALOX NAV SUPER 4Y HID M, release 12/04, subject to modifications Technical Information

L16X2

Abstract: ic logic gates
Contextual Info: pASIC 1 FAMILY ViaLink Technology Very-High-Speed CMOS FPGAs gj V ery H igh S p eed - V iaL ink m etal-to-m etal, program m able-via an ti­ fuse technology ensures useful internal logic function speeds at over 100 M H z, and logic cell delays o f under 2 ns.

DO-213AB MELF

Abstract: 12MMTAPE
Contextual Info: PACKAGING DATA Surface Mount Products BULK PACK QUANTITY PER CONTAINER PACKAGE PLASTIC BAGS VIALS DO-213AA MELF, LL34,SOD-80 5,000 500 DO-213AB (MELF, LL41) 5,000 500 TAPE & REEL PACKAGE TAPE WIDTH (MM) REEL SIZE (INCHES) 7 2,000 8 13 10,000 7 1,500 12 13

sod80

Contextual Info: CLD Packing options Leaded Devices BULK PACKED, ANTISTATIC BOX TAPED AND REELED, STANDARD AXIAL 2,500/BOX 2,500/REEL ADD BK SUFFIX ADD TR SUFFIX 1,000/VIAL 2,500/REEL 10,000/REEL ADD BK SUFFIX ADD TR SUFFIX ADD TR 13 SUFFIX Surface Mount Devices BULK PACKED, ANTISTATIC VIAL

report on PLCC

Abstract: 40673 plcc 68 QL8X12A reliability report solar cell Amorphous 40673 equivalent ql8x12 144TQFP PACKAGE QL8X12B
Contextual Info: SUMMARY August 1997 The pASIC device is a highly reliable Field Programmable Gate Array. The addition of the ViaLink to a CMOS process does not measurably increase the failure rate of the pASIC devices above that of normal CMOS logic products. The following is the summary of the High

ttl logic gates

Abstract: pASIC 1 Family ttl and gate
Contextual Info: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs FAMILY HIGHLIGHTS Very High Speed – ViaLink metal-to-metal, programmable-via antifuse technology ensures useful internal logic function speeds at over 100 MHz, and logic cell delays of under 2 ns.

QL12x16B

Abstract: ic 236
Contextual Info: Q L12x16B WildCat 2000 Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS .6000 total available gates, 88 input pins Q Very High Speed - ViaLink metal-to-metal programmable-via anti-fuse technology, allows counter speeds over 150 MHz and logic cell delays of