XLAUI Search Results

CEI11

Abstract: PRBS11 UG371 XC6VHX255T-FF1155 FPGA Virtex 6 Ethernet h8440 PRBS31 DSP48E1 FF1155 FF1923
Contextual Info: Virtex-6 FPGA GTH Transceivers User Guide UG371 v2.0 February 16, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or

Achronix Semiconductor

Contextual Info: I Speedster22i HD FPGA Family DS004 Rev. 2.6 – May 8, 2014 Preliminary Highlights • • • Advanced highest-density and highest‐bandwidth FPGA • Over 1.7 million effective look‐up‐tables • Abundant embedded hard IP for communica‐

a3568

Abstract: S-80141ALMC aplication notes w25q32b quanta 6320 XL710 26 Pin GPIO Connector Header Extender 90 Degree Angle TXAL 228 B
Contextual Info: Intel Ethernet Controller XL710 Datasheet Networking Division ND Revision: 2.1 December 2014 Legal Lines and Disclaimers No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a

PM 8038

Abstract: e/10Gb CDR
Contextual Info: TS-S10D166C Preliminary October, 2011 40Gb/s CFP Optical Transceiver Module SCF0400E4 Series 40Gbps 40km, 4-lane x 10Gb/s CWDM, DFB-LD, APD-PD Features  4-lane x 10Gb/s CWDM Optical Interface  High quality and reliability optical sub-assemblies 

Optical SAS QSFP

Abstract: CEI-6G-LR 28G-SR QSFP 32G CEI-11G QSFP QSFP CONNECTOR QSFP 25G ibis sata interlaken
Contextual Info: White Paper Extending Transceiver Leadership at 28 nm High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently supporting the subsequent increase in system bandwidth by attaining higher data

tcam

Abstract: ternary content addressable memory 100GbE Altera Stratix V datasheets of optical fpgas 100g phy interlaken network processor receiver ber fec 100G 40GBASE-R 10Gbase-kr transmitter
Contextual Info: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs WP-01128-1.1 White Paper As various standard bodies finalize their 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want

CS6051

Abstract: MAC+120G
Contextual Info: Product Brief CS605x Family of Transport Processors Key Features         Product Overview Transport and mapping of 100G, 40G, and 10G signals for OTN and Ethernet networks Aggregation & de-aggregation of up to ten 10GE/ODU2 e , and two 40GE/

Contextual Info: Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V4-5.1 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

tsmc design rule 40-nm

Contextual Info: Stratix IV Device Handbook Volume 1 Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.2 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

Contextual Info: Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.6 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

HSTL standards

Abstract: hard disk SATA pcb schematic hard disk SATA schematic 10G BERT ATX 2005 schematic diagram handbook texas instruments hd-SDI deserializer LVDS linear application handbook national semiconductor repeater 10g passive verilog code for max1619
Contextual Info: Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.0 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

ddr3 sata controller

Abstract: OC48 SSTL-15 SSTL-18 DFE EQUALIZER ERROR SCRAMBLE
Contextual Info: Section I. Device Datasheet and Addendum for Stratix IV Devices This section includes the following chapters: • Chapter 1, DC and Switching Characteristics for Stratix IV Devices ■ Chapter 2, Addendum to the Stratix IV Device Handbook Revision History

QT2225

Abstract: QT2025 TSMC 40nm qt2035 10G rj45 40GBASE-KR4 macsec 10G Ethernet PHy Xlaui 40GBASE-CR4
Contextual Info: 10G Datacom Product Line October, 2009 APPLIED MICRO PROPRIETARY AND CONFIDENTIAL Transport & Connectivity Roadmap DATACOM QT2025, QT2225 10G PHY 1/2-port XFP/SFP+/KR PHY 2/4-port SFP+ SR/KR PHY Triveni 10GBaseT 2/4-port 10GBASE-T PHY TELECOM Pemaquid Pemaquint

10Gb CDR

Abstract: BA rx transistor INF8077i Xlaui IC 555 architecture lc oscillator led based graphic equalizer ic P802 CEI-11G 11GSR
Contextual Info: Emerging Standards at ~10 Gbps for Wireline Communications and Associated Integrated Circuit Design and Validation An Invited Paper for CICC Mike Peng Li and Sergey Shumarayev Altera Corporation 101 Innovation Road San Jose, CA 95134 Abstract-We first review the signaling and jitter requirements

GPON block diagram

Abstract: TSMC 40nm 90 nm hspice CEI-6G-SR CPRI multi rate 10Gcapable 29K212 pcie X1 edge connector sata CIRCUIT diagram 40G-100G
Contextual Info: Innovating With a Full Spectrum of 40-nm FPGAs and ASICs with Transceivers WP-01078-1.4 White Paper Increasing bandwidth requirements for broadband services are driving silicon vendors to use more and more high-speed serial transceivers. Therefore, nextgeneration applications feature a wide range of data rates, from a few Mbps to

OC48

Abstract: SSTL-15 SSTL-18
Contextual Info: Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V4-4.9 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

pcie gen3

Abstract: 28gbps
Contextual Info: Stratix V Device Handbook Volume 1: Overview and Datasheet Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.2 11.0 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

HF35-F1152

Abstract: KF40-F1517 5sgxa3 eye-q 400 NF40-F1517 interlaken gf35 NF45 KF35-F1152
Contextual Info: Stratix V Device Family Overview January 2011 SV51001-1.6 SV51001-1.6 This document provides an overview of the Stratix V devices and their features. Many of these devices and features are enabled in the Quartus ® II software version 10.1. The remaining devices and features will be enabled in future versions of the

Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM DC to 11.3 Gbps per port, NRZ data rate Multitime constant, programmable receive equalization Compensates 25 inches of FR408 at 10.3125 Gbps Compensates 15 inches of FR408 at 11.3 Gbps 6-tap programmable transmit feedforward equalization FFE

Transistor hall s41

Abstract: CEI-11G QSFP connector Xlaui 10 gbps transceiver board card fci tsmc design rule 40-nm QSFP QSFP 40G transceiver pcie gen3
Contextual Info: White Paper FPGAs at 40 nm and >10 Gbps: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers This paper describes key technologies that enable Stratix IV GT FPGAs to deliver the performance and capabilities necessary to support 40G/100G applications with integrated 11.3-Gbps transceivers. These include the LC-based oscillator and decision-feedback equalization DFE at 40 nm for ultra-low jitter FPGA transceivers. Furthermore, the

lpddr2 datasheet

Abstract: lpddr2 QSFP optical active cable D-type Connector 25 Pin UniPHY lpddr2 CCPD 33 CB 100MHz lpddr2 spec tsmc 28nm standard io library lpddr2 phy lpddr2 DQ calibration
Contextual Info: Stratix V Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.0 July 2010 Copyright © 2010Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words

Optical Network Unit

Contextual Info: TS-S11D090B May, 2012 Preliminary Specification Serial 40Gb/s CFP Optical Transceiver Module SCF0420FRxNGG01 40GBASE-FR, VSR2000-3R2,1550nm EML, PIN-PD, SMF 2km Features Æ 40Gb/s Serial Optical Interface Ü High quality and reliability optical sub-assemblies

mini PCI express pcb

Abstract: hard disk SATA pcb schematic ATX 2005 schematic diagram mini-lvds source driver 4000 CMOS texas instruments Ethernet transceive 8-port GbE PHY pin number of ic cy 327 handbook texas instruments repeater 10g passive
Contextual Info: Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.1 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

Contextual Info: Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V4-5.3 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos