Z16C5010 Search Results

z16c50

Abstract: 16C50
Contextual Info: ZILOG INC <^04043 QDSSTDQ 2T7 blE D ZIL PRELIMINARY PRODUCT SPECIFICA TION Z16C50 D D PLL D ual D igital P h a se L ocked Loop M ic r o c o n t r o lle r FEATURES • Two independent Digital Phase Locked Loops in one package. ■ Synchronous status output

16C50

Contextual Info: p r elim in a r y p r o d u c t S p ec ific a tio n <£ZiIßö Z16C50 D u a l D ig it a l P h a s e L o c k e d L oo p FEATURES • Two independent Digital Phase Locked Loops in one package. ■ 10 MHz and 20 MHz Clock operation ■ Synchronous status output

16C50

Abstract: Biphase
Contextual Info: P r e l im in a r y p r o d u c t S p e c if ic a tion ^ZilßG Z16C50 D D P L L D u a l D ig it a l P h a s e L o c k ed L o o p M ic r o c o n t r o l l e r FEATURES • Two independent Digital Phase Locked Loops in one package. ■ Synchronous status output

Contextual Info: PRELIMINARY PRODUCT SPECIFICATION é^ Z iIîj G Z16C50 D D P LL D u a l D ig ita l P h a se L ocked L o o p M ic r o c o n t r o l l e r FEATURES • Two independent Digital Phase Locked Loops in one package. Synchronous status output Accept Code Violation input

Biphase

Abstract: 16C50 z16c50
Contextual Info: PRELIMINARY PRODUCT SPECIFICA TION Z16C50 D D P L L D u a l D ig it a l P h a s e L o c k e d L o o p M ic r o c o n t r o l l e r FEATURES • Two independent D igital Phase Locked Loops in one package. ■ 10 MHz and 20 M Hz C lock operation ■ Selectable clo ck rate, c lo ck sam pling edge, and data