Z8001 Search Results

25LS2521

Abstract: 25LS244 8051 interface 8155 8251 with 8086 9511A 6259A 8155 programmable peripheral interface 9517A AMZ8536 8253 interface with 8086 Peripheral
Contextual Info: MOS Microprocessor MOS Microprocessor Family Selector Guide 8086/88 8085A 8085A-2 8080A Z8001/2t Z8001/2-A Clock Parted 200ns 320ns 200ns Clock Generator 8284A On-Chip On-Chip 8224 8127 8127 Arithmetic Processing Unit 8087 9511A-1 9512-1 9 5Í1A -4 9512-1

nonseg

Contextual Info: Z8001 / Z8002® Military Z8000® CPU Central Processing Unit Military Electrical Specification 17 :1 M llO y September 1988 FEATURES • Regular, easy-to-use architecture ■ Instruction set more powerful than many minicomputers ■ Directly addresses 8

Z8002A

Abstract: scr LDK packages
Contextual Info: Z8001VZ8002* 16-Bit Microprocessors 2008Z/.L008Z DISTINCTIVE CHARACTERISTICS • • • 4, 6, 8 MHz CPU Clock High throughput with low system clock rate tor easi­ er system design Powerful General Register Architecture 16 general registers provide high throughput in all

Z8001ACE

Abstract: z8001aps Z8001PS Z8002BPS Z8002PS Z8002APS z8000cpu Z8010 Z8002 z8002cs
Contextual Info: Z8001/2 Z8000 CPU Central Processing Unit ùllO g Product Specification A pril 1985 i Regular, easy-to-use architecture • Instruction set m ore powerful than m any m inico m pu ters l Directly addresses 8 M bytes i Eight user-selectable addressin g m odes

Z8000

Contextual Info: P ro d u c t S p e c ific a tio n <£SL G E 1 Z8001 / Z8002® Z8000®CPU C entral Processing Unit October 1988 FEATURES Regular, easy-to-use architecture Instruction set m ore powerful than many m inicom puters R esource-shaping systems capabilities for

z0800206

Abstract: Z0800106 Z0800110 Z08002 Z0800 Z0800204CMB zilog z8001 1065D Z08002-06CMB TDA 2025
Contextual Info: ZIL06 INC 17E D • ^ 3 4 0 4 3 0013b77 T Z8001 / Z 80023 Military Z8000® CPU Central Processing Unit 17 '! - ^ Military Electrical Specification o -7 September 1988 FEATURES ■ Regular, easy-to-use architecture ■ Instruction set more powerful than many minicomputers

sbti

Abstract: z8001 Z8002 range-32768 RH1S z8000 family Z8001 package size Z8000 Z8001A CS zilog z8001
Contextual Info: Z8001/Z8002* 16-Bit Microprocessors Z008Z/.L008Z DISTINCTIVE CHARACTERISTICS Partitioned for Operating System Protection Hardware bit protects privileged instructions from ex­ ecution except by operating system. Supports 3 Types of Interrupts Separate pins provided for vectored, non-vectored

z160 amd

Abstract: hj 4094 Z8003 Z8010 Z8001 z8000cpu Z160 Z8000 Z8002 IR411
Contextual Info: P— 7 . 1 -l O ADVANCED INFORMATION f T P ro d u c t S p e c ific a tio n Z8001 IZ8002® Z8000® CPU Central Processing Unit October 1988 FEATURES • Regular, easy-to-use architecture ■ Instruction set more powerful than many minicomputers ■ Directly addresses 8 Mbytes

Contextual Info: «*»*?ÄäHä«SSSäii{$£ai Zilog ADVANCED INFORMATION P r o d u c t S p e c if ic a t io n Z8001 / Z8002® Z8000® CPU Central Processing Unit October 1988 FEATURES • Regular, easy-to-use architecture ■ Instruction set more powerful than many minicomputers

Z8002A

Contextual Info: <£SLO S P r o d u c t S pe cif icat ion 1 Z8001 / Z8002® Z8000®CPU Central Processing Unit October 1988 FEATURES • Regular, easy-to-use architecture ■ Instruction set m ore powerful than many m inicom puters ■ Directly addresses 8 M bytes ■ Eight user-selectable addressing m odes

Z8001 package

Abstract: Z8001 zilog z8001 PLCC80 PT01
Contextual Info: Package convertor PC ; 48 pos. Dip female socket with test points to 68 pos. PLCC plug. Pin assignment; specific for Zilog Z8001 micro controllers. 2.400" 0.200" 1.300" 0.600" 0.700" 0.300" 0.412" 0.216" 0.207" Relative Orientations DIP Pin 1 PLCC Pin 1 Substrate: FR4/G10, 0.0625"±0.007" thick.

Z8010

Abstract: LH8001 Z8000 Z8001 Z8002-CPU
Contextual Info: SHARP E L E K / f l ELEC DI V b? D • 01007=10 O OD G I I ? 2 ■ ¡ J-W-n-H» Z8001/Z8002 CPU LH 8001/LH 8002 Central Processing Unit Features ■ Regular, easy-to-use architecture. ■ Sophisticated interrupt structure. ■ Instruction set more powerful than many

LM 8002

Abstract: amz8000 Z8001 crystal OSCILATOR 4mhz Z8000 Z8002 AmZ8
Contextual Info: i Am8127 < AmZ8000 Clock Generator DISTINCTIVE CHARACTERISTICS Four TTL-level clocks G enerates synchronized TTL com patible clocks at 16MHz, 2M Hz and 1MHz to drive memory circuits and LSI peripheral devices. An additional TTL clock is synchronized with the CPU high-level clock for

the pin function of ic 7405

Abstract: AMZ8016-DMA
Contextual Info: 9 L 0 8 Z U IV AmZ8016 DM A T ransfe r C o ntroller DISTINCTIVE CHARACTERISTICS • • • Two independent multi-function channels Automatic loading/reloading of control parameters by each channel Optional automatic chaining of operations Channel interleave operations

Contextual Info: DMA Transfer Controller DISTINCTIVE CHARACTERISTICS • • Channel interleave operations Masked data pattern matching for search operations V ectored interrupts on selected transfer conditions Base registers for repetitive operations Tw o independent m ulti-function channels

Z- FIO

Abstract: dcp 4 z Z8038
Contextual Info: Z I L O G INC 17E D T1ÖM043 DD1E0Ô3 T " T -S £ -3 3 -D 3 Z8038/Z8538 FIO FIFO Input/ Output Interface Unit October 1988 Features • 128-byte FIFO buffer provides asynchronous bidirectional CPU/CPU or CPU/peripheral interface, expandable to any width in byte

sn76131

Abstract: tlo72cp TOSHIBA 2N3055 M53207P 2N3055 TOSHIBA KIA7313AP kia7640ap LA5530 M5L8155P TBB1458B
Contextual Info: ACTIVE ELECTRONICS COMPONENTS CROSS REFERENCE GUIDE 2SC429GTM 2SC458 2SC458LG 2SC503 2SC504 2SC510 2SC512 2SC519 2SC520A 2SC594 2SC699A 2SC780 2SC809-1 2SC945 2SC3012 2SC3074 2SC3114 2SC3115 2SC3116 2SC3117 2SC3134 2SC3135 2SC3138 2SC3143 2SC3144 2SC3145 2SC3157

Z8001-CPU

Abstract: Z8001 Z8010 Z8016 T-52-33-25 LH8010 Z6010 Z8000 Z8001CPU
Contextual Info: SHARP ELEK/ NELEC DIV h? D m&l&Qllò GD002D0 1 • D T -52 -3 3 -2 5 Z 8010 MMU LH 8010 M emory M anagem ent Unit Features ■ D ynam ic segm ent relocation makes software ad d resses in d ep en d en t of physical memory addresses. ■ S ophisticated access validation protects

Contextual Info: _ , M S G S-THOMSON 07C D | 7TST537 0 0 m a 3 2 0 I 67C 14596 D 7^55.- J 3 - J S P a g e d M em ory riV rr^ ^ T " " M a n a g e m e n t k • ^S z 8015pmiviü Unit Features • PMMU architecture supports multiprogramming systems and virtual memory implementations.

TDA0161 equivalent

Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
Contextual Info: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

Z8002 AB1V

Abstract: Z8001 Z8001 package size Z8000 Z8002 Z8001AB1V Z8001 AB1V heart rate monitor using ldr tda 2070 rh ix 0689
Contextual Info: 2 I I»»» r z 7 S G S -T H O M S O N Ä 7 # [ » [ R K s m i O T ® « ! Z 8001 S E G C P U Z8002 CPU CENTRAL PROCESSING UNIT • Regular, easy-to-use architecture. ■ Instruction set more powerful than many m ini­ computers. ■ Directly addresses 8 M bytes.

Z8001

Abstract: PLCC80
Contextual Info: 2.400" 0.100" 1.100" 0.600" 0.700" 0.200" 3 1 0.216" 0.423" Relative Orientations 4 DIP Pin 1 1 Substrate: 1.59mm ±0.18mm [0.0625" ±0.007"] FR4/G10 or equivalent high temp material. 17µm [1/2 oz.] Cu clad. SnPb plating. 3 Pins: shell material- Brass Alloy 360 1/2 hard;

Z8010

Abstract: GE rcrt Z8000 Z8010-MMU 1s463 zilog z8001
Contextual Info: ZILOG INC 17E D • 1^04043 G G i n i 4 T ii L i« « P ! R i P ;.^ rn.v^v^fiv'yfc n ii v in i"; P ro d u c tS p e c ific a tio n Z8010 Z8000 MMU Memory Management Unit October 1988 Features ■ Dynamic segment relocation makes software addresses independent of physical memory

Z8538

Abstract: 6N37
Contextual Info: < £ 2 iL G E Product Specification 1 Z8038/Z8538 FIO FIFO input/ Output Interface Unit The Z8538 is no longer offered. Features • 128-byte FIFO buffer provides asynchronous bidirectional CPU/CPU or CPU/peripheral interface, expandable to any width in byte