ZO 150 74 Search Results

Contextual Info: LH28F400SU B-ZO FEATURES • User-Configurable x8 or x16 Operation • 5 V Write/Erase Operation 5 V Vpp; 3.3 V Vqq - No Requirement for DC/DC Converter to Write/Erase • 150 ns Maximum Access Time (Vcc = 3.3 V ± 0.3 V) • Min. 2.7 V Read Capability - 160 ns Maximum Access Time

hc4351

Abstract: 74hc4053a 74HC4051
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA A n alo g M u ltip le x e rs / D e m u ltip le x e rs M C 5 4 /7 4 H C 4 0 5 1 M C 74H C 4052 M C 5 4 /7 4 H C 4 0 5 3 High-Performance Silicon-Gate CMOS The MC54/74HC4051, MC74HC4052 and MC54/74HC4053 utilize sili­ con—gate CMOS technology to achieve fast propagation delays, low ON

Contextual Info: DATA SHEET SKY65372-11: 699 to 748 MHz High Linearity, Active Bias Low-Noise Variable Gain Amplifier Applications Bypass Control • LTE, WCDMA, GSM wireless infrastructure  Low noise, high linearity systems  Macro base stations  Small cells RF_OUT

74HC4351

Abstract: Z1 DIODE
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C54/74HC4351 M C 54/74H C 4353 Analog M ultiplexers/ D em ultiplexers w ith Address Latch High-Perform ance Silicon-Gate CMOS J SUFFIX CERAMIC PACKAGE CASE 732-03 The MC54/74HC4351, and MC54/74HC4353 utilize silicon-gate CMOS

74F1056

Abstract: 74F1056SC C1995 M16A b50 diode
Contextual Info: 74F1056 8-Bit Schottky Barrier Diode Array General Description Features The ’F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines This device is designed to suppress negative transients caused by line reflections switching

circuit using 74hc4051

Abstract: HC4051 74HC4053 74HC4051 Motorola MC74HC4052 Germanium Schottky diode hc4053 MC74HC4052 HC4052 HC4351
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA A n alog M u ltip le x e rs / D e m u ltip le x e rs M C 5 4 /74 H C 4 0 5 1 M C 74H C 4052 M C 5 4 /7 4 H C 4 0 5 3 High-Performance Silicon-Gate CMOS The MC54/74HC4051, MC74HC4052 and MC54/74HC4053 utilize sili­ con—gate CMOS technology to achieve fast propagation delays, low ON

Avantek UT

Abstract: AVANTEK t-74-13-01
Contextual Info: AVANTEK INC QbE Q | A A V A N T E K I E I \ im n b k S| MSA-0170 T-74-13-01 MODAMP Cascadable Silicon Bipolar Monolithic Microwave Integrated Circuit Amplifiers Avantek 70 mil Package Features • • • • Cascadable 500 Gain Block Usable Gain to 4.5 GHz

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Analog M u ltip lexers/ D em u ltip lexers w ith Address Latch M C 54/74H C 4351 M C 54/74H C 4353 High-Performance Silicon-Gate CMOS The M C54/74HC4351, and MC54/74HC4353 utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low

74F1056

Abstract: 74F1056SC M16A 8-bit schottky diode
Contextual Info: Revised August 1999 74F1056 8-Bit Schottky Barrier Diode Array General Description Features The 74F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed

FCT1280

Abstract: 072AC 74FCT128
Contextual Info: QSFCT280T, 1280T e High Speed CMOS 9-Bit Parity Generator/Checker qs54/74fct28ot q s 54/74f c t i 2bot FEATURES/BENEFITS • QSFCT280BT faster than FAST • QSFCT1280T has 18 enable, registered outputs • Io l = 48 mA COM, 32 mA MIL • TTL-compatible input and output levels

74F1056

Abstract: M16A 74F1056SC
Contextual Info: 74F1056 8-Bit Schottky Barrier Diode Array General Description The ’F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed to suppress negative transients caused by line reflections, switching

Light-Dependent Resistor specification

Abstract: photoresistor ldr 07 photoresistor LDR 03 photoresistor LDR 5mm 5mm ldr photo resistor LDR 07 CDS LDR 5mm photoresistors cadmium sulfide photoresistor LDR 03 PHOTO RESISTOR
Contextual Info: TOKEN GENERAL PURPOSE RESISTORS General Purpose Wire Wound / Fusible Resistors Token Electronics Industry Co., Ltd. Taiwan: No. 137, Sec. 1, Chung Shin Rd., Wu Ku Hsiang, Taipei Hsien, Taiwan, R.O.C TEL: 886-2-2981 0109; FAX: 886-2-2988 7487 China: 12F, Zhongxing Industry Bld., Chuangye Rd., Nanshan District, Shenzhen, Guangdong

74HC4052A

Contextual Info: MOTOROLA SC {LO G IC} 05 MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC4051 MC54/74HC4052 MC54/74HC4053 Advance Information Analog M ultiplexers/ Dem ultiplexers J SUFFIX CERAMIC CASE 620-09 High-Performance Silicon-Gate CMOS The MC54/74HC4051, MC54/74HC4052, and MC54/74HC4053 utilize silicon-gate

Photoresistor rohs

Abstract: photoresistor LDR 03 Light-Dependent Resistor specification cadmium sulfide photoresistor photoresistor LDR 1000
Contextual Info: TOKEN GENERAL PURPOSE RESISTORS General Purpose Wire Wound / Fusible Resistors Token Electronics Industry Co., Ltd. Taiwan: No. 137, Sec. 1, Chung Shin Rd., Wu Ku Hsiang, Taipei Hsien, Taiwan, R.O.C TEL: 886-2-2981 0109; FAX: 886-2-2988 7487 China: 12F, Zhongxing Industry Bld., Chuangye Rd., Nanshan District, Shenzhen, Guangdong

Contextual Info: 74SSTUB32868 www.ti.com SCAS835 – JUNE 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST • FEATURES • • • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout 1-to-2 Outputs Supports Stacked DDR2 DIMMs

Contextual Info: 74SSTUB32868 www.ti.com SCAS835 – JUNE 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST • FEATURES • • • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout 1-to-2 Outputs Supports Stacked DDR2 DIMMs

q28b

Contextual Info: 74SSTUB32868A www.ti.com SCAS846 – JULY 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST • FEATURES • • • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout 1-to-2 Outputs Support Stacked DDR2 DIMMs

Contextual Info: 74SSTUB32868A www.ti.com SCAS846 – JULY 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST • FEATURES • • • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout 1-to-2 Outputs Support Stacked DDR2 DIMMs

p q1a

Contextual Info: 74SSTUB32868 www.ti.com SCAS835 – JUNE 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST • FEATURES • • • • • • • • Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR2 DIMM PCB Layout 1-to-2 Outputs Supports Stacked DDR2 DIMMs

Contextual Info: DATA SHEET PRELIMINARY ICS853111 ICS853111 Integrated DIFFERENTIAL-TO-2.5V/3.3V LOW SKEW, 1-TO-10 Circuit Systems, Inc. BUFFER LVPECL/ECL FANOUT LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853111 is a low skew, high performance 1-to-10 Differential-to-2.5V/3.3V LVPECL/

WQFN0202-8V

Contextual Info: HSG2002 SiGe HBT High Frequency Medium Power Amplifier REJ03G0444-0100 Rev.1.00 Oct.28.2004 Features • High Transition Frequency fT = 28.5 GHz typ. • Low Distortion and Excellent Linearity P1dB at output = +25 dBm typ. f = 5.8 GHz • High Collector to Emitter Voltage

74ALVCH16832

Abstract: 74ALVCH16832DGG JESD22-A114 JESD22-A115 JESD78
Contextual Info: INTEGRATED CIRCUITS 74ALVCH16832 7-bit to 28-bit address register/driver with 3-state outputs Product data File under Integrated Circuits — ICL03 Philips Semiconductors 2001 Dec 14 Philips Semiconductors Product data 7-bit to 28-bit address register/driver with 3-state

Contextual Info: PRELIMINARY Integrated Circuit Systems, Inc. ICS853111A LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853111A is a low skew, high performance 1-to-10 Differential-to-2.5V/3.3V LVPECL/ HiPerClockS

ICS853111

Abstract: ICS853111-02 MC100EP111 MC100LVEP111
Contextual Info: PRELIMINARY Integrated Circuit Systems, Inc. ICS853111-02 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853111-02 is a low skew, high performance 1 - t o - 10 Differential-to-2.5V/3.3V HiPerClockS