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    ZX54AHCT Search Results

    ZX54AHCT Datasheets (87)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    ZX54AHCT00J
    		Zytrex Quad 2-Input NAND Gates Scan PDF
    ZX54AHCT00N
    		Zytrex Quad 2-Input NAND Gates Scan PDF
    ZX54AHCT01J
    		Zytrex Quad 2-input NAND Gates with Open Drain Outputs Scan PDF
    ZX54AHCT01N
    		Zytrex Quad 2-input NAND Gates with Open Drain Outputs Scan PDF
    ZX54AHCT02J
    		Zytrex Quad 2-Input NOR Gates Scan PDF
    ZX54AHCT02N
    		Zytrex Quad 2-Input NOR Gates Scan PDF
    ZX54AHCT03J
    		Zytrex Quad 2-Input NAND Gates with Open Drain Outputs Scan PDF
    ZX54AHCT04J
    		Zytrex Hex Inverters Scan PDF
    ZX54AHCT05J
    		Zytrex Hex Inverters with Open Drain Outputs Scan PDF
    ZX54AHCT08J
    		Zytrex Quad 2-Input AND Gate Scan PDF
    ZX54AHCT09J
    		Zytrex Quad 2-Input AND Gates with Open Drain Outputs Scan PDF
    ZX54AHCT107J
    		Zytrex Dual J-K Negative Edge Triggered Flip-Flop with Clear Scan PDF
    ZX54AHCT109J
    		Zytrex Dual J-K Positive Edge Triggered Flip-Flops with Preset and Clear Scan PDF
    ZX54AHCT10J
    		Zytrex Triple 3-Input NAND Gates Scan PDF
    ZX54AHCT112J
    		Zytrex Dual JK Negative Edge Triggered Flip-Flops with Preset and Clear Scan PDF
    ZX54AHCT11J
    		Zytrex Triple 3-Input AND Gates Scan PDF
    ZX54AHCT121J
    		Zytrex Monostable Multivibrators with Schmitt Trigger Inputs Scan PDF
    ZX54AHCT123J
    		Zytrex Dual Retriggerable Monostable Multivibrator Scan PDF
    ZX54AHCT12J
    		Zytrex Triple 3-Input NAND Gates with Open Drain Outputs Scan PDF
    ZX54AHCT138J
    		Zytrex 3-Line to 8-Line Decoders / Multiplexers Scan PDF

    ZX54AHCT Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    74AHCT

    Abstract: AHCT193
    Contextual Info: Z y tre x ZX54AHCT ZX74AHCT 193 Synchronous 4-Bit Up/Down Binary Counters with Dual Clock February 1965 OBJECTIVE SPECIFICATIONS Features Description m Look-ahead circuitry enhances cascaded These are high-speed synchronous reversible 4-bit bina­ ry counters. Synchronous operation is provided by hav­


    OCR Scan     		ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT AHCT193 PDF

    74AHCT

    Abstract: AHCT174
    Contextual Info: Mrex ZX54AHCT g ZX74AHCT I February 1985 g M C L ZX54AHCT § ZX74AHCT § f # Hex/Quad D-Type Flip-Flops with Clear OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74ALS logic family The '174 contains six, and the '175 contains tour D-type


    OCR Scan     		ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT AHCT174 PDF

    74AHCT

    Contextual Info: Z y t r e ZX54AHCT § ZX74AHCT M x Ê Ê Triple 3-Input AND Gate^ February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pln-out, speed and drive compatibility with 54/74ALS logic family These devices contain three independent 3-input AND


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT PDF

    74AHCT

    Contextual Info: Z v tre x ZX54AHCT § ZX74AHCT M February 1985 g # _ % 4-Bit D-Type Registers with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • Gated output control lines for enabling or disabling the outputs These 4-bit registers contain D-type flip-flops with 3-state


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT PDF

    150a gto

    Abstract: 198S 74AHCT
    Contextual Info: Zvtrex # _% ZX54AHCT ZX74AHCT M February 1985 Dual 1-of-4 Decoder/Multiplexers OBJECTIVE SPECIFICATIONS Features Description • Designed specifically for high-speed memory decoders and data transmission systems These devices are designed to be used in high-perform ­


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: ahcti39 74AHCT 54AHCT Ta--55Â 150a gto 198S PDF

    74AHCT

    Abstract: PF1016
    Contextual Info: Zvtrex ZX54AHCT ZX74AHCT February 1985 534 Octal D-Type Flip-Flops with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pln-out, speed and drive compatibility with 54/74ALS logic family ■ Low power consumption characteristic of


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT PF1016 PDF

    zytrex

    Abstract: 74AHCT
    Contextual Info: Sftmx ZX54AHCT ZX74AHCT February 1985 OBJECTIVE SPECIFICATIONS 157 sag158 Quad 2-Line to 1-Line Data Se/ector/Muitipiexers _ Features Description • Function, pin-out, speed and drive compatibility with 54/74ALS logic family These are data selector/m ultiplexers which select a 4-bit


    OCR Scan     		ZX54AH ZX74AHCT 54/74ALS 74AHCT: 54AHCT: AHCTi57 AHCTi58 74AHCT 54AHCT Cl-50 zytrex PDF

    AHCT148

    Abstract: 74AHCT
    Contextual Info: Zvtrex ZX54AHCT § ZX74AHCT M February 1985 M 8-Line to 3-Line Priority Encoders OBJECTIVE SPECIFICATIONS _ Features Description • Encodes eight data lines in priority The '148 provides three bits of binary coded output rep­ resenting the position of the highest order active input,


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: AHCT148 74AHCT PDF

    UFN 432

    Abstract: 74AHCT
    Contextual Info: Zvtrex ZX54AHCT ZX74AHCT OBJECTIVE SPECIFICATIONS Features Description • Multiplexed I/O ports provides improved bit density These eight-bit universal registers feature multiplexed I/O ports to achieve full eight-bit data handling. Two function-select inputs and two output-control Inputs can


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS UFN 432 74AHCT PDF

    74AHCT

    Abstract: BV 724 C
    Contextual Info: Z v t r e ZX54AHCT M ZX74AHCT x February 1985 Quad 2-Input AND Gates with Open-Drain Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74ALS logic family These devices contain four independent 2-Input AND


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT BV 724 C PDF

    Zytrex

    Abstract: 74AHCT Zytrex 74ahct
    Contextual Info: Zyfrex ZX54AHCT ZX74AHCT Octal Buffers and Line Drivers with 3-State Outputs February 1985 OBJECTIVE SPECIFICATIONS 540 SS&541- ' Features Description m Function, pln-out, speed and drive The ’540 and ’541 are general purpose high-speed octal tine drivers/buffers with 3-state outputs. The inputs and


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: Zytrex 74AHCT Zytrex 74ahct PDF

    74AHCT

    Contextual Info: Zvtrex ZX54AHCT ZX74AHCT f/ #_0^ Quad 2-Input NAND Gates with Open-Drain Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74ALS logic family These devices contain four independent 2-input NAN D


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT PDF

    74AHCT

    Abstract: TTL Schmitt-Trigger cmos BC5-10
    Contextual Info: Zytrex ZX54AHCT ZX74AHCT February 1985 121 Monostable Multivibrators with Schmitt-Trigger inputs OBJECTIVE SPECIFICATIONS Features Description • Schmitt-trigger for slow input transitions ■ Internal timing resistor These multivibrators feature dual negative-transition-trig­


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT TTL Schmitt-Trigger cmos BC5-10 PDF

    ahct245

    Abstract: 74AHCT Zytrex
    Contextual Info: Zyfrex ZX54AHCT ZX74AHCT M February 1985 ^ M Octal Bus Transceivers with 3-State Outputs OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74ALS logic family These high-speed octal bus transceivers are designed


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: ahct245 74AHCT Zytrex PDF

    74AHCT

    Contextual Info: Z y f r e ZX54AHCT ZX74AHCT M x February 1985 8-Bit Parailel-ln/Serial-Out Shift Registers with Clear OBJECTIVE SPECIFICATIONS Features Description • Synchronous load These devices feature parallel-in or serial-in, serial-out registers, gated clock inputs and an overriding clear in­


    OCR Scan     		ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT PDF

    74AHCT

    Contextual Info: Z v tre x ZX54AHCT ¡ M M ZX74AHCT M g M Dual J-K Negative-Edge-Triggered Flip-Flops with Clear February 1985 OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility with 54/74ALS logic family These devices contain two independent J-K negativeedge-triggered flip-flops. A low level at the CLR input


    OCR Scan     		ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT PDF

    74AHCT

    Abstract: Zytrex 74
    Contextual Info: hrirex ZX54AHCT ZX74AHCT Februa ry 1985 74 Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear OBJECTIVE SPECIFICATIONS Features Description Function, pin-out, speed and drive compatibility with 54/74ALS logic family Low power consumption characteristic of


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT Zytrex 74 PDF

    PF1016

    Abstract: 74AHCT
    Contextual Info: Zvfrex ZX54AHCT ZX74AHCT . V j Octal D-Type Transparent Latches with 3-State Outputs February 1985 OBJECTIVE SPECIFICATIONS Features Description • 8 latches in a single package The '5 3 3 co n sists o f 8 h igh -spe ed D -type latch es c o u ­ pled to 3-state o u tp u t bu ffers w ith high d riv e c u rre n t c a ­


    OCR Scan     		54/74ALS 74AHCT: 54AHCT: ZX54AHCT ZX74AHCT PF1016 74AHCT PDF

    74AHCT

    Contextual Info: Ks T u Æ Ê W i w m • ÊÊ W r m Cyc.y\ ,'J ^ jrjf',c i rJArt/S Q A ? C , Pp{. r February1985 j i ZX54AHCT tJZ X W H C T f i l Ë Quad 2-lnput NAND Gate4 v Open-Drain Outputs1 s p é c ia tio n s Features Description ■ Function, pin-out, speed and drive


    OCR Scan     		I-JZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT PDF

    74AHCT

    Abstract: S593 BC116 TI 593
    Contextual Info: Zvfrex ZX54AHCT ZX74AHCT 5 9 2 %%&593 8-Bit Binary Counter with Input Register and 8-Bit Binary Counter with Bidirectional input Register/Counter Outputs F e brua ry 1985 OBJECTIVE SPECIFICATIONS Description Features Wide operating voltage range: 4.5V to 5.5V


    OCR Scan     		ZX74AHCT S4/74ALS 74AHCT: 54AHCT: 74AHCT S593 BC116 TI 593 PDF

    74AHCT

    Contextual Info: Z y tr e x ZX54AHCT ZX74AHCT 191 Synchronous 4-Bit Up/Down Binary Counters Februa ry 1985 OBJECTIVE SPECIFICATIONS tion eliminates the output counting spikes normally asso­ ciated with asynchronous ripple clock counters. Features • Single down/up count control line


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT PDF

    74AHCT

    Contextual Info: Z y t r e ZX54AHCT § ZX74AHCT M x February 1985 f Dual J-K Positive Edge-Triggered Flip-Flops with Preset and Clear OBJECTIVE SPECIFICATIONS Features Description • Function, pln-out, speed and drive compatibility with 54/74ALS logic family These devices contain two positive-edge-triggered J-K


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT PDF

    74AHCT

    Contextual Info: Z v tre x ZX54AHCT ZX74AHCT February 1985 590 8-Bit Binary Counter with 3-State Output Register OBJECTIVE SPECIFICATIONS Features Description • Function, pin-out, speed and drive compatibility wjth 54/74ALS logic family The ’5 9 0 contains an 8-bit binary counter which feeds an


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT PDF

    74AHCT

    Contextual Info: Z vtrex ZX54AHCT / ZX74AHCT § 8-Bit Serial-ln/Parallel-Out Shift Registers February 1985 OBJECTIVE SPECIFICATIONS Features Description • AND-Gated enable/disable serial inputs These are high-speed 8-bit shift registers with AND-gated serial inputs and an asynchronous clear. Data is en­


    OCR Scan     		ZX54AHCT ZX74AHCT 54/74ALS 74AHCT: 54AHCT: 74AHCT PDF