ZXXXXXX Search Results

Winbond 29EE011

Abstract: Q953 29EE011 W29EE011P-90/15
Contextual Info: W29EE011 xfflTv Electronics Corp. 128K x 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29EE011 is a 1-megabit, 5-volt only CMOS flash memory organized as 128K x 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V p p is

Contextual Info: MAY 8 1992 Data Sheet March 1992 i =AT&T Microelectronics ATT7C185 High-Speed CMOS SRAM 64 Kbits 8K x 8 Common I/O, Output Enable Features • Highspeed — 10 ns maximum access time ■ Plug-compatible with IDT7164 and CY7C185/186 ■ Automatic powerdown during long cycles

cd-rom repair diagram

Abstract: Z86E33
Contextual Info: ZiLOG Confidential Document Number: Page 1 of 4 Revision: 00 DRAFT Objective Spec ZSBCEMW0100ZCO EMIT Z8 SDK Software Development Kit Definition: An internal document that describes an evaluation kit or development kit. Includes a complete description of the kit contents,

CS8415A

Abstract: Pulse Transformer AES3 CDB8415A CP1201 CS8415A-CZ CS8415A-CZR CS8415A-CZZ IEC60958 IEC-60958 IEC60958-4
Contextual Info: CS8415A 96 kHz Digital Audio Interface Receiver Features General Description ! Complete EIAJ CP1201, IEC-60958, AES3, The CS8415A is a monolithic CMOS device which receives and decodes one of 7 channels of audio data according to the IEC60958, S/PDIF, EIAJ CP1201, or

spice 74ls00

Contextual Info: CircuitMaker for Windows Integrated Schematic Capture and Circuit Simulation User Manual CircuitMaker 6 CircuitMaker PRO Revision C Information in this document is subject to change without notice and does not represent a commitment on the part of MicroCode Engineering. The software described in this document is

B1581

Abstract: B1379 bl238
Contextual Info: CMOS SyncBiFlFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 • • • • • • • • • • FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident sim ultaneous reading and writing of data on a single clock edge is perm itted

CDB8427

Abstract: CP1201 CS8427 CS8427-CS CS8427-CSZ CS8427-CZ CS8427-DS CS8427-DZ IEC-60958 CS84XX
Contextual Info: CS8427 96 kHz Digital Audio Interface Transceiver Features General Description z Complete EIAJ CP1201, IEC-60958, AES3, S/PDIF-compatible Transceiver z +5.0 V Analog Supply VA+ z +3.3 V or +5.0 V Digital Interface (VL+) The CS8427 is a stereo digital audio transceiver with

Contextual Info: Part Number Index Part no. Page Part no. Page 01P0601 24 AD0670R 10 02P0XXX 24 AD 07XXX 7 0 3 P06 0 3 24 AD071AUK 04P0XXX 24 AD 08XXX 06P0XXX 24 AD09XXX 1771P 145 24 AD0910UK Part no. Page Part no. Page 6 BRLZ-12 15 C12M XXX 31 L Z U S3 X X X LZ U S4 X X X

aes3 receiver

Abstract: CS8420-CSZ TRANSISTOR SMD MARKING CODE 1d CDB8420 CS8420 CS8420-CS CS8420-CSR CS8420-CSZR CS8420-DSZ IEC60958
Contextual Info: CS8420 Digital Audio Sample Rate Converter Features General Description Complete IEC60958, AES3, S/PDIF, EIAJ CP1201-compatible Transceiver with Asynchronous Sample Rate Converter Flexible 3-wire Serial Digital I/O Ports 8-kHz to 108-kHz Sample Rate Range

82358

Abstract: XC96 8251 intel microcontroller architecture F245B intel 82358 INTERFACING OF 8272 WITH 8086 EISA chip set 82355 ta 8271 hq intel 82355
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed fo r use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 M b ytes/S ec Maximum Data

m514256

Abstract: M514256A MCM514256AP70 M514256A-80 MCM514256AP80 MCM514256AJ70 M514 MCM514256AJ70R2 M51425 L42S
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM514256A MCM51L4256A 256K x 4 Bit CMOS Dynamic RAM Page Mode, Commercial and Industrial Temperature Range The M C M 514256A is a 1 .0 ^ CM OS high-speed dynam ic random access memory. It is organized as 262,144 four-bit w ords and fabricated w ith C M OS silicon-gate pro­

TMS4464

Abstract: TMS 2764 Texas Instruments IC mk4564 mcm6256 tms4500a Fuji Electric tv schematic diagram ET 439 power module fuji mcm6665 74L5138 TMS4500
Contextual Info: SMYOOO2 . ,MOS Memory Data Book 1984 II I III \' h' \/ Commercial and Military , :\ Specifications ' 1'/ ! . .Jf TEXAS INSTRUMENTS Alphanumeric Index, Table of Contents, Selection Guide Interchangeability Guide _ Glossary/Timing Conventions/Data Sheet Structure

Contextual Info: RT9170 1. 1.1 Intelligent T1 Controller INTRODUCTION 1.2 SUMMARY * The Rockwell RT9170 Intelligent T1 Controller is a micro­ processor MPU controlled device which implements a T1 interlace between the multiplexed digital DS1 signal and the PCM highway of digital voice and data system equip­

Contextual Info: m i c r o e l e c t r o n i c s group Lucent Technologies Bell Labs Innovations ORCA OR2CxxA 5.0 V and OR2TxxA (3.3 V) Series Series Field-Programmable Gate Arrays Features 2 • Flip-flop/latch options to allow programmable prior­ ity of synchronous set/reset vs. clock enable

CDB8415A

Abstract: CP1201 CS8415A CS8415A-CS CS8415A-CZ CS8415A-IS CS8415A-IZ IEC60958 IEC-60958
Contextual Info: CS8415A 96 kHz Digital Audio Interface Receiver Features General Description z Complete The CS8415A is a monolithic CMOS device which receives and decodes one of 7 channels of audio data according to the IEC60958, S/PDIF, EIAJ CP1201, or AES3. The CS8415A has a serial digital audio output

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT MC-421000A32BA, 421000A32FA 1 M-WORD BY 32-BIT DYNAMIC RAM MODULE FAST PAGE MODE Description The MC-421000A32BA, 421000A32FA are 1,048,576 w ords by 32 bits dynam ic RAM m odule on w hich 2 pieces o f 16 M DRAM: /¿PD4218160 are assembled.

Contextual Info: CS8415A 96 kHz Digital Audio Interface Receiver Features General Description  Complete EIAJ CP1201, IEC-60958, AES3, The CS8415A is a monolithic CMOS device which receives and decodes one of 7 channels of audio data according to the IEC60958, S/PDIF, EIAJ CP1201, or

CS8420-CSZR

Abstract: AES3 Pulse Transformer AES3 TRANSISTOR SMD MARKING CODE 1d CDB8420 CP-1201 CS8420 IEC60958 rtxp CS8420-CSZ
Contextual Info: CS8420 Digital Audio Sample Rate Converter Features General Description  Complete IEC60958, AES3, S/PDIF, EIAJ The CS8420 is a stereo digital audio sample rate converter SRC with AES3-type and serial digital audio inputs, AES3-type and serial digital audio outputs, and

Contextual Info: CS8420 Digital Audio Sample Rate Converter Features General Description Ł Complete IEC60958, AES3, S/PDIF, EIAJ The CS8420 is a stereo digital audio sample rate converter SRC with AES3-type and serial digital audio inputs, AES3-type and serial digital audio outputs, and

XC90

Abstract: intel 82358
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data

transformerless power supply using scr

Abstract: AN22 CDB8427 CP1201 CP-1201 CS8427 IEC60958 IEC-60958 IEC60958-4 ABS grade validity
Contextual Info: CS8427 96 kHz Digital Audio Interface Transceiver Features General Description  Complete EIAJ CP1201, IEC-60958, AES3, S/PDIF-compatible Transceiver  +5.0 V Analog Supply VA+  +3.3 V or +5.0 V Digital Interface (VL+)  Flexible 3-wire Serial Digital I/O Ports

S72 SMD

Abstract: tu34 qml-38535 001T smd marking S72
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED REV SHEET REV SHEET 15 16 17 REV STATUS OF SHEETS 18 REV SHEET PMIC N/A STANDARD M ICRO CIRC UIT DRAW ING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE 8 PREPARED BY

Contextual Info: CMOS SyncBiFlFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 IDT723614 Integrated Device Technology, Inc. FEATURES: • Free-running C LKA and CLKB can be asynchronous or coincident sim ultaneous reading and writing of data on a single clock edge is permitted

Contextual Info: PRELIMINARY KM732V688/L 64Kx32 Synchronous SRAM 64K X 32 - Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • • • • • • • • • • • • • • • • Synchronous Operation. 2 Stage Pipelined operation with 4 Burst On-Chip Address Counter.