0025FC Search Results

d 1556 transistor

Contextual Info: • bbS3T31 0025fc.Qfl ISM « A P X N AMER PHILIPS/DISCRETE BSS64 b?E 3> HIGH VOLTAGE N-P-N TRANSISTORS Silicon planar epitaxial transistor in a microminiature plastic envelope intended for application in thick and thin-film circuits. This transistor is intended fo r high-voltage general purpose and switching

CY7B9910

Abstract: CY7B9920
Contextual Info: fax id: 3516 CY7B9910 CY7B9920 Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines

Contextual Info: CY7B991 CY7B992 PRELIMINARY CYPRESS SEMICONDUCTOR Programmable Skew Clock Buffer PSCB Features Functional Description • Output pair skew < 100 ps typical (250 max.) • All outputs skew <250 ps typical (500 max.) • 3.75- to 80-MHz output operation • User-selectable output functions

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

CY7B991

Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 ps maximum ■ 3.75 MHz to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns

Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 maximum ■ 3.75 to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns ❐ Inverted and non-inverted

Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 maximum ■ 3.75 to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns ❐ Inverted and non-inverted

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 W ances as low as 50 while delivering miniĆ mal and specified output skews and fullĆ swing logic levels CY7B9910 TTL or CY7B9920 CMOS . Features D All outputs skew <100 ps typical (250 max.) D D D D D D D 15Ć to 80ĆMHz output operation

Contextual Info: MITSUBISHI LSIs M 5 M 4 V 1 6 1 6 0 B J ,T P ,R T - 6 ,- 7 ,- 8 ,- 6 S ,- 7 S ,- 8 S _ FAST PAGE MODE 16777216-BIT 1048576-WQRP BY 16-BIT DYNAMIC RAM DESCRIPTION This is a family of 1048576-word by 16-bit dynamic RAMS, fabricated with the high performance CMOS process,and is ideal for

CY7B991-7JI

Abstract: CY7B991 7B991 CY7B992 CY7B991-7LMB
Contextual Info: 92 CY7B991 CY7B992 Programmable Skew Clock Buffer Features functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can

Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 ps maximum ■ 3.75 MHz to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns

7B991

Abstract: CY7B991 CY7B992 MS2525
Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Features functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can

CY7B991

Abstract: program plc xf0 CY7B992 todc
Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Features Functional Description • All Output Pair Skew <100 ps Typical 250 ps maximum ■ 3.75 MHz to 80 MHz Output Operation ■ User Selectable Output Functions ❐ Selectable Skew to 18 ns ❐ Inverted and Non-inverted

Contextual Info: TOSHIBA- TC514900AJL70/80 524,288 WORD X 9 BIT DYNAMIC RAM DESCRIPTION The TC514900AJL is the new generation dynamic RAM organized 524,288 word by 9 bit. The TC514900AJL utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit techniques

Contextual Info: CYPRESS SEMICONDUCTOR b5E T> 2 5 0 ^ 2 QQ1Q7T2 CYP CY7B991 CY7B992 PRELIMINARY CYPRESS SEMICONDUCTOR TÔ2 P rogram m ab le Skew C lock B u ffer P S C B Functional Description • Output pair skew <100 ps typical (250 max.) • All outputs skew <250 ps typical

tb99

Abstract: 005133a 0021336 CY78991 5 CY7B991 CY7B992 LOW11 RMS141
Contextual Info: fax id: 3515 CY7B991 CY7B992 CYPRESS Programmable Skew Clock Buffer PSCB Features • All output pair skew <100 ps typical (250 max.) • 3.75- to 80-MHz output operation • User-selectable output functions — Selectable skew to 18 ns — Inverted and non-inverted

CY7B991-5JC

Abstract: CY7B991 7B991 CY7B992
Contextual Info: fax id: 3515 1CY 7B9 92 CY7B991 CY7B992 Programmable Skew Clock Buffer PSCB Features functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can

Contextual Info: CY7B991 CY7B992 Programmable Skew Clock Buffer Programmable Skew Clock Buffer Features Functional Description • All output pair skew <100 ps typical 250 ps maximum ■ 3.75 MHz to 80 MHz output operation ■ User selectable output functions ❐ Selectable skew to 18 ns

Contextual Info: fax id: 3516 CY7B9910 CY7B9920 Low Skew Clock Buffer Block Diagram Description Featu res Phase Frequency Detector and Filter • All outputs skew <100 ps typical 250 max. • 1 5 -to 80-MHz output operation These two blocks accept inputs from the reference frequency

50T23

Contextual Info: fax id: 3515 CY7B991 CY7B992 Programmable Skew Clock Buffer PSCB functions. These multiple-output clock drivers provide the sys­ tem integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual driv­

Contextual Info: CY7B9910 CY7B9920 PRELIMINARY Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows

CY7B9910

Abstract: CY7B9920
Contextual Info: CY7B9910 CY7B9920 Low Skew Clock Buffer Features Block Diagram Description • All Outputs Skew <100 ps typical 250 max. Phase Frequency Detector and Filter ■ 15 to 80 MHz Output Operation ■ Zero Input to Output Delay ■ 50% Duty Cycle Outputs ■ Outputs drive 50Ω terminated lines