20CG1 Search Results

Contextual Info: n n iii n . CMOS Programmable Electrically Erasable Logic Device A l W l l l a Semiconductors Pmduct Preview »m PEEL 20CG10-15 — Synchronous preset, asynchronous clear — Independent programmable output enables Features • Advanced CM O S EEPROM Technology

Contextual Info: S4E D 4040707 DDQ1D50 ÖTb « I C T I C T INC , INC._ PEEL 20CG1 OA-15/PEEL™ 20CG1OAL-15 CMOS Programmable Electrically Erasable Logic Device Features T 'M b - i'î 'Ç n • Architectural Rexfciirryr I — 92 product term X 44 input AND array

Contextual Info: INTERNATIONAL C M O S MÔ4D7Q7 00DQ3SÖ 1 37E D Product Preview INTERNATIONAL CMOS TECHNOLOGY, INC. PEEL 20CG10-12/PEEL 20CG10=15 CMOS Programmable Electrically Erasable Logic Device Features • 1 Micron CMOS EEPROM Technology Architectural Flexibility — 92 product temi X 44 input AND array

PEEL20CG10

Abstract: 20CG10 PEEL 20Cg10 PALC20G10
Contextual Info: PEEL 20CG10 AMI SEMICONDUCTORS CMOS Programmable Electrically Erasable Logic Device Features February 1993 General Description The AMI 20CG10 is a CMOS Programmable Electrically Erasable Logic device that provides a highperformance, low-power, reprogrammable,

PEEL20CG10

Abstract: PALC20G10
Contextual Info: AMI PEEL 20CG10 SEMICONDUCTORS CMOS Programmable Electrically Erasable Logic Device Features February 1993 General Description The AMI 20CG10 is a CMOS Programmable Electrically Erasable Logic device that provides a highperformance, low-power, reprogrammable,

Contextual Info: , INC. PEEL 20CG1 OA-15/PEEL™ 20CG1OAL-15 C M O S Program m able Electrically Erasable Logic Device F e a tu re s • Advanced CMOS EEPROM Technology ■ Architectural Flexibility — 92 product term X 44 input AND array — Up to 22 inputs and 10 outputs

PEEL20CG10AJ-15

Contextual Info: Commercial/ Industrial INC.- PEEL 20CG10A -5/-7/-10/-15/L-15/-25 CMOS Programmable Electrically Erasable Logic Features Architectural Flexibility — 92 product term X 44 input AND array — Up to 22 inputs and 10 outputs — Up to 12 configurations per macrocell

Contextual Info: INTERNATIONAL C M O S 5SE D 4flMQ707 DOOQMl 2 Product Preview INTERNATIONAL CMOS TECHNOLOGY, INC. 7 PEElIM 20CG10-12/PEE! 20CG1 0-15 CMOS Programmable Electrically Erasable Logic Device Features • 1 Micron CMOS EEPROM Technology Architectural Flexibility

Contextual Info: PEEL 20CG10 AMI SEMICONDUCTORS CMOS Programmable Electrically Erasable Logic Device General Description Features The AMI 20CG10 is a CMOS Programmable Electrically Erasable Logic device that provides a highperformance, low-power, reprogrammable, and architecturally enhanced alternative to conventional

Contextual Info: INTERNATIONAL CMOS TECHNOLOGY, INC. Preliminary Data March 1989 TM Features Advanced CMOS EEPROM Technology High Performance, Low Power Consumption — tPD = 20ns, fmax= 37MHz — Icc = 55mA + 0.5mA/MHz EE Reprogrammability — Low risk reprogrammable inventory

Contextual Info: Preliminary Data INTERNATIONAL CMOS TECHNOLOGY, INC. INTERNATIONAL C M O S 37E D H March 1991 4640707 0D0043T 1 IS ICT PEEL 22CV10A CMOS Programmable Electrically Erasable Logic Device Featu res ^ ^ ^ ~<^~7 Architectural Flexibility — 132 product term x 44 input AND array

Contextual Info: GO UL D INC/ 6 0 U L D A M I •> GOULD A/HiLSemiconductors MOE D MOSS'Jib D O l E T ö B b ■ A M I CMOS Programmable Electrically Erasable Logic Device PEEL 20CG10 T-46-19 -07 Features ~\ Application Versatility — Replaces random SSI/MSI logic — Emulates 24-pin bipolar PAL devices

Contextual Info: Advanced Commercial INC. PEEL 20CG1 OA -5 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility — 92 product term X 44 input AND array — Up to 22 inputs and 10 outputs — Up to 12 configurations per macrocell — Synchronous preset, asynchronous clear

Contextual Info: iET , INC. PEEL 22CV1 OA-10/PEEL™22CV1 OA-15 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility — 132 product term x 44 input AND array — Up to 22 inputs and 10 outputs — Variable product term distribution 8 to

22CV10AP

Abstract: 22cv10 nte quick cross ict peel 18CV8J palce programmer schematic blackjack vhdl code PA7140J-20 INTEL PLD910 PALCE610
Contextual Info: Data Book General Information PEEL Arrays PEEL Devices Special Products and Services Development Tools Application Notes and Reports Package Information PLACE Users Manual_ Introduction to PLACE PLACE Installation Getting Started with PLACE Operation Reference Guide

Contextual Info: •> g o u l d A M I * Semiconductors CMOS Programmable Electrically Erasable Logic Device PEEL 20CG10 Features • A pplication Versatility — Replaces random SSI/MSI logic — Emulates 24-pin bipolar PAL devices — Convert 24-pin PAL and EPLD designs with

Contextual Info: ET INC. Industrial PEEL 20CG1 OAI -10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features Industrial Grade Specifications — Vcc = 4.5V to 5.5V, TA = -40°C to 85°C — Reprogrammable 24-pin DIP, SOIC and 28-pin PLCC packages Architectural Flexibility

Contextual Info: SME 3> 4040707 0001040 =157 M I C T I C T INC , INC. PEEL 20CG10-25 ' ‘4 fe- W - 01 CMOS Programmable Electrically Erasable Logic Device Features • Advanced CMOS EEPROM Technology ■ High Performance, Low Power Consumption — tPD = 25ns, fmax= 33.3MHz

Contextual Info: , INC._ PEEL 20CG10-25 CMOS Programmable Electrically Erasable Logic Device Features Advanced CMOS EEPROM Technology High Performance, Low Power Consumption — tp D = 25ns, fmax= 33.3MHz — Ice = 55mA + 0.5mA/MHz

Contextual Info: Preliminary Data INTERNATIONAL CMOS TECHNOLOGY, INC. March 1991 PEEL 22CV10A CMOS Programmable Electrically Erasable Logic Device Features • Advanced CMOS EEPROM Technology Architectural Flexibility — 132 product term x 44 input AND array — Up to 22 inputs and 10 outputs

Contextual Info: , INC._ PEEL 20CG1 OA-10/PEEL™20CG1 OA-15 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility — 92 product term X 44 input AND array — Up to 22 inputs and 10 outputs — Independently programmable

Contextual Info: K T Commercial INC. PEEL 20CG1 OA -7/-10/-15/L-15/-25 CMOS Programmable Electrically Erasable Logic Device Features Architectural Flexibility — 92 product term X 44 input AND array — Up to 22 inputs and 10 outputs — Up to 12 configurations per macrocell

Contextual Info: INC. PEEL 20CG10-25 CMOS Programmable Electrically Erasable Logic Device Features • Advanced CMOS EEPROM Technology ■ Architectural Flexibility — 92 product term X 44 input AND array — Up to 22 inputs and 10 outputs — Independently programmable

allmax

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