20P2V Search Results

MS-013AC

Abstract: SOP20 Package SOP20-P-375-1 20P2V-A
Contextual Info: 20P2V-A Plastic 20pin 375mil SOP EIAJ Package Code SOP20-P-375-1.27 JEDEC Code MS-013AC Weight g 0.48 Lead Material Cu Alloy e 11 E Recommended Mount Pad 1 10 Symbol F A D A2 A1 b y L e L1 HE e1 I2 20 b2 c Detail F A A1 A2 b c D E e HE L L1 y b2 e1 I2 Dimension in Millimeters

4000B

Abstract: 74LS374 M74HC374 M74HC374DWP M74HC374P M74HC534
Contextual Info: M IT S U B IS H I HIGH S P E E D C M O S M 74H C374P M 74H C 374D W P O C T A L 3 -S T A T E N O N IN V E R T IN G D -T Y P E F L IP -F L O P DESCRIPTION The M 74H C 374 is a sem ico ndu ctor integrated c irc u it con­ PIN CONFIGURATION TOP VIEW sisting of eight p o s itiv e -e d g e trig g e re d D -type flip -flo p s

M74HC244P

Abstract: 4000B 74LS244 M74HC244 M74HC244DWP 74LS244 PIN diagram
Contextual Info: M IT S U B IS H I HIGH S P E E D CM O S M 74H C244P M 74H C244DW P O C T A L 3 -S T A T E N O N IN V E R T IN G B U F F E R /L IN E D R IV E R /L IN E R E C E IV E R DESCRIPTION T h e M 7 4 H C 2 4 4 is a sem iconductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW

74LS273

Abstract: M74HC273P 4000B M74HC273 M74HC273DWP pin diagram of 74ls273
Contextual Info: M IT S U B IS H I HIGH S P E E D C M O S M 74H C 273P M 74H C 273D W P O C T A L D -T Y P E F L IP - F L O P W IT H C O M M O N C L O C K A N D R E S E T DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74H C 273 is a sem iconductor integrated circuit con­

hex head with sw 19

Abstract: 24P2E
Contextual Info: READ/WRITE AMPLIFIER OF THIN FILM HEAD FOR HDD SEM OPERATES WITH A SINGLE 5V POWER SUPPLY. EMPLOYS 24-PIN SSOP SUITABLE FOR COMPACT HDD c o h w k to r M52882FP D E S C R I P T I O suitable for com pact HDDs. The device has achieved the low input capacitance 18pF and low input

432W6

Abstract: 48P4B hssop 44P3W-R 28P0 5P5T tsop 2-54 42P9R 70P3S-M 479F7G
Contextual Info: MITSUBISHI INTEGRATED CIRCUIT PACKAGES LIST OF PACKAGE CODES CLASSIFIED ACCORDING TO PIN NUMBER 1. LIST OF PACKAGE CODES CLASSIFIED ACCORIDING TO PIN NUMBER Pin Count Structure Type Lead Pitch mm 5 P P P P P P C C P P P C P P P P P P P P C P P P P P P P

Contextual Info: MITSUBISHI -CDGTL LOGIC} Tl Î>ÊÏ h2M1ÛE7 00l24Tfi □ T MITSUBISHI ALSTTLs M74ALS258P ^ QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER W ITH 3-STATE OUTPUT (INVERTED 6249827 MITSUBISHI 9 1D 12498 CDGTL LOGIC) DESCRIPTION The M 74ALS258P is a sem iconductor integrated cir­

00155L

Contextual Info: .^ 0«° M 74 ALS 534 P " 7 ^ ^ -O *7'¿ » S ' MITSUBISHI ALSTTLs OCTAL D-TYPE EDGE-TRIGGERED FLIP FLOP W ITH 3-STATE OUTPUT INVERTED _ 624982 7 MITSUBISHI <DGTL LOGIC) DESCRIPTION 91D 12559 D PIN CONFIGURATION (TOP VIEW) The M74ALS534P is a semiconductor intergrated circuit

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1035P TËJ MITSUB ISH I {DGTL LOGIC} Q012732 G | HEX NONINVERTING BUFFER W ITH OPEN COLLECTOR OUTPUT / DESCRIPTION PIN CONFIGURATION TOP VIEW ” T h e M 7 4 A L S 1 0 3 5 P is a s e m ic o n d u c to r in te g ra te d c ir­ c u it c o n s is tin g o f six n o n -inverting b u ffe rs w ith open

Contextual Info: M IT S U B IS H I <DIGITAL ASSP> M 74HC240-1P/FP OCTAL 3-S T A T E IN V E R TIN G B U F F E R /L IN E D R IV E R /L IN E R E C E IV E R DESCRIPTION T h e M 7 4 H C 2 4 0 -1 is a n in te g r a te d c irc u it c h ip c o n s is tin g of PIN CONFIGURATION TOP VIEW

ci la 7610

Contextual Info: c +e MITSUBISHI ALSTTLs . op,00° M 74A L S 620A -1P v ie N v t ^s ^ - 3 _ OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI CDGTL LOGIC) DESCRIPTION The M74ALS6Í20A-1P is a semiconductor integrated cir­ cuit consisting of eight bus transm itter/receiver circuits

M74ALS09

Abstract: M74ALS74 dd127 M74ALS257 M74ALS05 m74als32 m74als561 m74als245 20P2V M74ALS04
Contextual Info: MITSUBISHI íDGTL L0GIC3- TI ]>ËÏ bSMTBE? 0 0 i a 4 3 c] 1 T • ■ MITSUBISHI ALSTTLs M74ALS175P ”6 2 4 9 8 2 / MITSUBISHI DGTL LOGIC 91D 1 2 43 9 D QUADRUPLE D-TYPE FLIP FLOP W ITH RESET DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M 74ALS175P is a sem iconductor integrated circuit

Contextual Info: M ITSU B ISH I HIGH S P E E D CMOS M 74H C 688P/FP/D W P 8-BIT E Q U A L I T Y CO M P A R A T O R DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74H C 688 is a sem iconductor integrated circuit con­ sisting of an 8 -b it d igital com parator w ith a cascade input.

ci la 7610

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A LS 6 5 1 P 7 -52-3/ OCTAL BUS TRANSCEIVER/REGISTER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI 91 D 12674 (DGTL LOGIC ) DESCRIPTION The M74ALS651P is a semiconductor integrated circuit consisting of eight bus transceiver/registers with 3-state

m74als191p

Contextual Info: ÍDGTL LOGIC} 91D TI De | 12446 b241fl27 □ 0 1 2 4 4b ñ r D MITSUBISHI ALSTTLs M 74A LS191P SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER W ITH MODE CONTROL • 7 ^ V ' 5 ' ' ^ >3 DESCRIPTION - o 7 PIN CONFIGURATION TOP VIEW Th e M 7 4 A L S 1 9 1 P is a s e m ic o n d u c to r in te g ra te d c irc u it

8 pin dip j k flipflop ic

Abstract: M74ALS04
Contextual Info: M IT S U B IS H I A L S T T L s , M 7 4 A L S 6 4 0 A - 1 P - 7 - - 5 3 .- 3 1 OCTAL BUS TR A N SC EIVER W IT H 3 -S T A T E O U TPU T IN V E R T E D ' 6249827 MITSUBISHI (DGTL L O GI C) DESCRIPTION The M 74ALS640A-1P is a semiconductor integrated cir­

Contextual Info: MITSUBISHI ALSTTLs _ . M MI TSU BISHI -CDGTL LOGIC} 7 4 A L S I Q lit! DEl bdnocc U Duìcvià â P h flT~ HEX INVERTING BUFFER W ITH OPEN COLLECTOR OUTPUT 7 ^ DESCRIPTION / 3 - / ^ PIN CONFIGURATION TOP VIEW Th e M 7 4 A L S 1 0 0 5 P is a s e m ic o n d u c to r in te g ra te d c ir­

74ALS640

Contextual Info: MITSUBISHI -CDGTL LOGIC} dT | ba^flS? D O i a k b B 4 M ITSUBISHI A L ST T Ls sc* -s s 5 " : . M 7 4 A LS6 4 7 P ,o.9B OCTAL BUS TR A N SC EIV ER /R EG IST ER WITH OPEN COLLECTOR OUTPUT NONINVERTED 6249827 MITSUBISHI CDGTL LOGTC) DESCRIPTION The M74ALS647P is a semiconductor integrated circuit

M74ALS374P

Abstract: dd127 4d40t
Contextual Info: MITSUBISHI iDGTL LOGIC} TI 1mF | bSLHÖ27 D0155E5 5 MITSUBISHI ALSTTLs ,oC* M 74A LS374P OCTAL D-TYPE EDGE-TRIGGERED FLIP FLOP W ITH 3-STATE OUTPUT NONINVERTED 6249827 MITSUBISHI 9 1D 12525 (DGTL LOGIC) DESCRIPTION D PIN CONFIGURATION (TOP VIEW) T h e M 7 4 A L S 3 7 4 P is a s e m ic o n d u c to r in te g ra te d c irc u it

l54c

Abstract: DT070
Contextual Info: MITSUBISHI ÍDGTL LOGIC} "il Ï Ë | ^24^027 0012303 O j ~ MITSUBISHI ALSTTLs M 7 4 A L S 1 1 4 A P T “ 9 6 > ’O t7 ~ O t7 • _ DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP-FLOP W ITH SET. COMMON RESET AND COMMON CLOCK 6249827 MITSUBISHI CDGTL LOGIC DESCRIPTION

Contextual Info: MITSUBISHI ALSTTLs i # O C * “ M 7 4 A L S 6 Z 3 A - 1 P -7 ^ 5 2 - 3 / OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT NONINVERTED 6249827 MITSUBISHI CDGTL LOGIC) DESCRIPTION The M74ALS623A-1P is a semiconductor integrated circuit c o n s is tin g of eight bus transm itter/receiver

D0-15L

Abstract: LS74AD
Contextual Info: 7 z1 % > -'0 '7 -¿ ? S ' M 74ALS873AP ¡C' 3< DUAL 4 -B IT D-TYPE TRANSPARENT LATCH W ITH 3-STATE OUTPUT NONINVERTED 50t° CDGTL LOGIC) DESCRIPTION PIN CONFIGURATION (TOP VIEW) DIR EC T RESET , p " IN P U T I M ° O UTPUT } -q C O N TR O L IN PU T E c

74ALS131

Abstract: 74als245a m74als138p 74als169b 74ALS193D
Contextual Info: M IT S U B IS H I -CDGTL L O G I C } TI 0 F | b E 4 ciflE 7 0 D lE 3 flt b |~ _ 6249827 MITSUBISHI I M IT SU B ISH I ALSTTLs M 74ALS131P <DG T L LO GI C 91D 12386 D 3 -L IN E TO 8 -L IN E D E C O D E R /D E M U L T IP L E X E R W IT H A D D R E S S R E G IS T E R

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A L S 1 0 0 2 À P a D eE| tk24=]aS7 0015712 > | MITSUBISHI IDGTL LOGIC} 11 QUADRUPLE 2-IN P U T PO SITIVE NOR BUFFER 7 ^ V 3 - /S DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M74ALS1002AP is a semiconductor integrated cir­ cuit consisting of four 2-input positive-logic NOR buffer