311MHZ Search Results

CK16

Abstract: STM-64 VSC8173 multiplexer transponder
Contextual Info: 9.9-10.7Gb/s 16:1 Multiplexer with Clock Generator VSC8173 Physical Layer Products Product Brief Features: • Fully Compliant with OIF 99.102 • SONET/SDH Jitter Compliant • 311MHz or 622MHz Data Clock Input Modes • Superior Data Output Eyes • Low Power 1.5W Typ

Contextual Info: 2.5V, 2GHz ANY DIFF. IN-TO-LVDS Precision Edge SY89872U PROGRAMMABLE CLOCK DIVIDER/FANOUT Final BUFFER WITH INTERNAL TERMINATION FEATURES DESCRIPTION • Guaranteed AC performance over temperature and voltage: • >2GHz FMAX • < 750ps Tpd matched delay between banks

SY89871U

Abstract: SY89872U SY89873L SY89873LMG SY89873LMI SY89873LMITR
Contextual Info: Precision Edge 3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS SY89873L ® Precision Edge PROGRAMMABLE CLOCK DIVIDER SY89873L FANOUT BUFFER W/ INTERNAL TERMINATION Micrel, Inc. FEATURES • Guaranteed AC performance • > 2.0GHz fMAX output toggle • > 3.0GHz fMAX input

621L

Abstract: SY58620L SY58621L SY58621LMGTR
Contextual Info: SY58621L Precision 3.2Gbps CML/LVPECL Backplane Transceiver with Integrated Loopback General Description The SY58621L is a low jitter, high-speed transceiver with a variable swing LVPECL transmitter buffer and a CML high-gain receiver optimized for precision telecom

7809 voltage regulator datasheet

Abstract: 7809 voltage regulator voltage regulator 7809 INL03991-02 7809 data sheet national semiconductor embedded system projects pdf free download toshiba web cam TB62705 ST 7809 voltage regulator excalibur Board
Contextual Info: & News Views Second Quarter 2001 Newsletter for Altera Customers Altera Provides the Complete I/O Solution with the New APEX II Device Family Altera introduces the APEXTM II device family— flexible, high-performance, high-density programmable logic devices PLDs that deliver

Contextual Info: 78P2254 STM-1/STS-3 Transceiver JUNE 2002 DESCRIPTION FEATURES The 78P2254 is a transceiver IC designed for 155.52Mbit/s STS-3 or STM-1 transmission. It is used at the interface to a 75Ω coaxial cable using CMI coding. Interfacing to digital framer circuits is

30021

Abstract: L48C L41C IC L44C DATASHEET L30C l31c L43C ORSO42G5 ORSO82G5 ORT42G5
Contextual Info: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs August 2005 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and

Achronix Semiconductor

Contextual Info: I Speedster22i HD FPGA Family DS004 Rev. 2.6 – May 8, 2014 Preliminary Highlights • • • Advanced highest-density and highest‐bandwidth FPGA • Over 1.7 million effective look‐up‐tables • Abundant embedded hard IP for communica‐

Contextual Info: 2.5V, 2GHz ANY DIFF. IN-TO-LVDS Precision Edge PROGRAMMABLE CLOCK DIVIDER/FANOUT SY89872U FINAL BUFFER WITH INTERNAL TERMINATION FEATURES • Guaranteed AC performance over temperature and voltage: • >2GHz FMAX • < 750ps Tpd matched delay between banks

SY58620L

Abstract: SY58620LMG SY58620LMGTR SY58621L
Contextual Info: SY58620L Precision 4.25Gbps CML Backplane Transceiver with Integrated Loopback General Description The SY58620L is a low jitter, high-speed transceiver with a variable swing CML transmitter buffer and a CML high-gain receiver optimized for precision telecom and

SY89871U

Abstract: SY89872U SY89873L SY89873LMG SY89873LMI SY89873LMITR Sonet Clock Generator
Contextual Info: Precision Edge 3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS SY89873L ® Precision Edge PROGRAMMABLE CLOCK DIVIDER SY89873L FANOUT BUFFER W/ INTERNAL TERMINATION Micrel, Inc. FEATURES • Guaranteed AC performance • > 2.0GHz fMAX output toggle • > 3.0GHz fMAX input

texas handbook

Abstract: 1008-B
Contextual Info: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.

Broken Conductor Detection for Overhead Line Distribution System

Abstract: verilog code for CORDIC to generate sine wave verilog code for cordic algorithm for wireless la TXC 13.56 sma diode h5c intel 945 motherboard schematic diagram 2005Z fet k241 EARTH LEAKAGE RELAY diagram schematic diagram for panasonic inverter air cond
Contextual Info: Stratix GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com SGX5V1-1.2 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

cd 1619 CP

Abstract: RX SOP 1738 bc 494 b f.m transmitter Schematics AL 1450 DV hp 2212 sdc 2025 AL 2450 dv circuit diagram toggle switches 2041 BY TRANSISTOR BC 187 vhdl code for 16 prbs generator
Contextual Info: Stratix II GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIIGX5V1-4.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

qfn-44 PACKAGE footprint

Contextual Info: KIT ATION EVALU E L B AVAILA 19-2215; Rev 6; 10/07 +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis The MAX3892 serializer is ideal for converting 4-bitwide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFO

DMX RECEIVER

Abstract: UA 741 datasheet GR-253 VSC8150
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet 2.488Gb/s SONET/SDH Overhead Monitor VSC8150 Features • Integrated 2.488 Gb/s Demultiplexer • LOF/SEF Alarm Generation • Outputs SONET/SDH Transport Overhead • Serial Data Loopthrough Output

3pin variable resistor pin connection

Abstract: 621l SY58620L SY58621L SY58621LMGTR pin configuration 25K variable resistor
Contextual Info: SY58621L Precision 3.2Gbps CML/LVPECL Backplane Transceiver with Integrated Loopback General Description The SY58621L is a low jitter, high-speed transceiver with a variable swing LVPECL transmitter buffer and a CML high-gain receiver optimized for precision telecom

S3040

Abstract: S3041 S3042 S3045 STS-48
Contextual Info: DEVICE SPECIFICATION SONET/SDH/ATM OC-48 1:8 RECEIVER BiCMOS LVPECL OC-12 CLOCK1:8 GENERATOR SONET/SDH/ATM OC-48 RECEIVER AND RECEIVER TRANSMITTER FEATURES GENERAL DESCRIPTION • Micro-power Bipolar technology • Complies with Bellcore and ITU-T specifications

Contextual Info: IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS INDUSTRIAL TEMPERATURE RANGE IDT5T929 NRND PRECISION CLOCK GENERATOR OC-48 APPLICATIONS NOT RECOMMENDED FOR NEW DESIGNS FEATURES: DESCRIPTION: • Input frequency: - For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,

192MHZ

Contextual Info: ABX0213 192MHz – 400MHz Low Phase Noise PECL XO 12 – 25MHz Crystal FEATURES • • • • Low phase noise output for the 192MHz to 400MHz range (-134 dBc at 10kHz offset). PECL output. 12 to 25MHz crystal input. Integrated crystal load capacitor: no external

pc keyboard ic

Abstract: altera stratix ii ep2s60 circuit diagram bc 327 K.D carrier detect phase shift finder 15.21 pcie gen 2 payload SIIGX52006-1 free transistor equivalent book DIODE ED 34 transistor bd 242
Contextual Info: Stratix II GX Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SIIGX5V2-4.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

pin configuration of 7496 IC

Abstract: TMS 3617 Transistor TT 2246 ttl to mini-lvds EP2C35F672 IC 4033 pin configuration EP2C20F256 CI 4017 combinational digital lock circuit projects EP2C8F256
Contextual Info: Cyclone II Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CII5V1-3.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

free transistor equivalent book

Abstract: HD-SDI over sdh 3D123 CEI 23-16 Chapter 3 Synchronization diode handbook GX 010 texas handbook transistor DATA REFERENCE handbook vhdl code for 16 prbs generator
Contextual Info: Stratix II GX Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SIIGX5V2-4.3 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

SF3838B315M00B200A00

Contextual Info: Surface Acoustic Wave SAW Filters 300MHz Band SAW Filters for RKE SF3838B315M00C300A01/ SF3838B315M00B200A00 Features How to Order SF 3838 B 315M00 C 300 A01 • RF filter for RKE (Remote Keyless Entry) • Miniature size and light weight • Excellent temperature characteristics