4007J Search Results

Contextual Info: H C R O N SEM ICONDUCTOR INC b7E D • blllS4'i ODOTÖMT T47 ■ URN PRELIMINARY M T4LC 4007J S " JM E Gx4 D R A M MICRON I s e » .c o m > u !:to i« c DRAM 1 MEG x 4 DRAM 3.3V EDO PAGE MODE, OPTIONAL SELF REFRESH FEATURES • • • • • • • •

EDO DRAM

Abstract: MT4C4007JDJ-6L MT4C4007JDJ-6
Contextual Info: 1 MEG x 4 EDO DRAM V IIC Z R C H V S DRAM M T4C 4007J FEATURES PIN ASSIGNMENT (Top View Single+5V ±10% power supply JEDEC-standard pinout and packages High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL-compatible Refresh modes: RAS#-ONLY, CAS#-BEFORE- RAS#

Contextual Info: PRELIMINARY 4007J S 1 MEG X 4 DRAM DRAM 1 MEG x 4 DRAM 3.3V EDO PAGE MODE, OPTIONAL SELF REFRESH FEATURES • • • • • • • • • • Single +3.3V ±0.3V power supply Low power, 250|xW standby; lOOmW active, typical JEDEC-standard pinout and packages

4c4007

Abstract: 4007J
Contextual Info: 4007J L 1 MEG X 4 DRAM |u iic n o N 1 MEG x 4 DRAM DRAM 5V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH FEATURES PIN ASSIGNMENT (Top View) • • • • • S in g le + 5 V ± 1 0 % p o w er su p p ly JE D E C -sta n d a rd p in o u t and p ack ag es H ig h -p erfo rm a n ce C M O S silico n -g ate process

LIS-1024

Contextual Info: OBSOLETE M I C R O N 1 ^cnllvZ DRAM E G x 4 4007J FEATURES PIN ASSIGNMENT Top View • • • • • Single +5V +10% pow er supply JED EC-standard pinout and packages H igh-perform ance CM OS silicon-gate process All inputs, outputs and clocks are TTL-com patible

MT4C4007JDJ-7

Abstract: MT4C4007JDJ7 marking 3GY MRP21
Contextual Info: PRELIMINARY iimiy—a n i v f wlt4C40Q7J S t MEG x: 4 DRAM 1 MEG x 4 DRAM DRAM 5V, EDO PAGE MODE, OPTIONAL SELF REFRESH ] MATURES • Single +5V ±10% pow er supply ■ JED EC-standard pinout and packages ■ High-performance C M O S silicon-gate process