128MS Search Results

ECHO canceller IC

Abstract: audio echo cancellation ic E1 PCM encoder Echo Processor IC G164 MCS51 MT9122 MT9122AE MT9122AP RP10
Contextual Info: CMOS MT9122 Dual Voice Echo Canceller Preliminary Information with Tone Detection ISSUE 5 Features • • • • • • • • • • • • • Ordering Information MT9122AP 28 Pin PLCC MT9122AE 28 Pin PDIP -40 °C to + 85 °C Dual channel 64ms or single channel 128ms

Contextual Info: NJU26902 Digital Audio Delay ̈ Package ̈ General Description The NJU26902 is a digital audio delay. The NJU26902 provides delay-time adjustment function and digital audio interface. NJU26902V ̈ FEATURES • 2-Channel Audio Delay 24 bits data width . Delay Time 85msec at fs = 48kHz ( 128msec at fs = 32kHz , 43msec at fs = 96kHz)

Contextual Info: MT4C1004J S 4 MEG X 1 DRAM |U|CRON 4 MEG x 1 DRAM DRAM 5V, STANDARD OR SELF REFRESH •n FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C1004J) or 128ms (MT4C1004J S only) • Industry-standard pinout, timing, functions and packages • High-perform ance CM OS silicon-gate process

Echo Processor IC

Abstract: ssci 890 EP11 EP12 MCS-51 MT9123 MT9123AE MT9123AP RP10 RP15
Contextual Info: CM O S MITEL MT9123 Dual Voice Echo Canceller Prelim inary Inform ation Features _ ISSUE 1_ O ctober 1996 Dual channel 64m s or single channel 128ms echo cancellatio n O rdering Inform ation M T9123AP 28 Pin PLCC M T9123AE

Contextual Info: CMOS MT9123 Dual Voice Echo Canceller Data Sheet Features • ISSUE 1 Dual channel 64ms or single channel 128ms echo cancellation Ordering Information MT9123AP 28 Pin PLCC MT9123AE 28 Pin PDIP -40 °C to + 85 °C • Conforms to ITU-T G.165 requirements •

K2667

Contextual Info: MT93L00A Multi-Channel Voice Echo Canceller Preliminary Information Features • • • • • • • • • • • • • • • • • DS5525 Independent multiple channels of echo cancellation; from 32 channels of 64ms to 16 channels of 128ms with the ability to mix

Contextual Info: MT9300B Multi-Channel Voice Echo Canceller Advance Information Features • • • • • • • • • • • • • • • • • • DS5385 Independent multiple channels of echo cancellation; from 32 channels of 64ms to 16 channels of 128ms with the ability to mix

TDG 2003

Abstract: PCM encoder
Contextual Info: ZL50233 4 Channel Voice Echo Cancellor Data Sheet Features • October 2003 Independent multiple channels of echo cancellation; from 4 channels of 64ms to 2 channels of 128ms with the ability to mix channels at 128ms or 64ms in any combination Ordering Information

Contextual Info: CMOS MT9123 Dual Voice Echo Canceller Preliminary Information Features • • • • • • • • • • • • ISSUE 1 Dual channel 64ms or single channel 128ms echo cancellation Conforms to ITU-T G.165 requirements Narrow-band signal detection Programmable double-talk detection threshold

G164

Abstract: MCS51 MT9122 MT9122AE MT9122AP RP10 RP15
Contextual Info: CMOS MT9122 Dual Voice Echo Canceller Preliminary Information with Tone Detection Features • • • • • • • • • • • • • ISSUE 5 Dual channel 64ms or single channel 128ms echo cancellation Conforms to ITU-T G.165 requirements ITU-T G.165/G.164 disable tone detection

Contextual Info: MT4C1004J L 4 MEG X 1 DRAM (M IC R O N DRAM 4 MEG x 1 DRAM 5V, FAST PAGE MODE, OPTIONAL EXTENDED REFRESH FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C1004J) or 128ms (MT4C1004J L only) • Industry-standard pinout, timing, functions and packages

Contextual Info: MT4C4001 J L 1 MEG X 4 DRAM (M IC R O N DRAM 1 MEG x 4 DRAM DRAM STANDARD OR LOW POWER, EXTENDED REFRESH FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J L) • Industry-standard x4 pinout, timing, functions and packages

Contextual Info: MT4C4001 J S 1 MEG X 4 DRAM (MICRON DRAM 1 MEG x 4 DRAM 5V, STANDARD OR SELF REFRESH • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J S) • Industry-standard pinout, timing, functions and packages • High-perform ance CM OS silicon-gate process

mt4c1004j

Abstract: MT4C1004
Contextual Info: MT4C1004J L 4 MEG X 1 DRAM (MICRON DRAM 4 MEG x 1 DRAM FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C1004J) or 128ms (MT4C1004J L only) • Industry-standard x l pinout, tim ing, functions and packages • High-performance C M O S silicon-gate process

MN675201

Abstract: xo 405 me MN6750165 QFP084-P-1818E
Contextual Info: □ MN6750165 / 245 / 325 / 405 MN6750165 / 245 / 325 / 405 1Type 1ROM x8-bit 1RAM (x8-bit) 1Minimum Instruction Execution Time 16K/24K/32K/40K 384/512/640/768 0.5ms (at 4.5 to 5.5V, 8MHz) 128ms (at 3.0 to 5.5V, 8MHz, operates in fosc/256) (Operation with 32.768kHz by Mask Option)

T4C4001JDJ-6

Abstract: mt4c4001
Contextual Info: MT4C4001 J S 1 MEG X 4 DRAM [M IC R O N DRAM 1 MEG X 4 DRAM FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (M T4C4001J S) • Industry-standard pinout, timing, functions and packages • High-perform ance CM O S silicon-gate process

marking wml

Abstract: j-l003 marking WMM C1994 MT4C4001 MT4C4001J MT4C4001JDJ-6
Contextual Info: M ir n O M I .“ hT M T 4C 4001J S 1 M EG X 4 D R A M 1 MEG DRAM X 4 DRAM STANDARD OR SELF REFRESH a J3 > FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J S) • Industry-standard pinout, timing, functions and packages

adaptive filter noise cancellation

Abstract: E1 PCM encoder MCS51 MT9123 MT9123AE MT9123AP RP10 RP12 RP15 implement codec G.711
Contextual Info: CMOS MT9123 Dual Voice Echo Canceller Preliminary Information Features • • • • • • • • • • • • ISSUE 1 Dual channel 64ms or single channel 128ms echo cancellation Conforms to ITU-T G.165 requirements Narrow-band signal detection Programmable double-talk detection threshold

IC TDA 0200 sp

Contextual Info: CM OS MT9122 Dual Voice Echo Canceller with Tone Detection Preliminary Information M ITEL Features • • • • • • • • • • _ IS S U E 5_ Septem ber 1996 Dual channel 64ms or single channel 128ms echo cancellation

Contextual Info: 1 MEG X 4 FPM DRAM MICRON I TECHNOLOGY. INC. DRAM M T4C 4001J FEATURES • 1,024-cycle refresh distributed across 16ms MT4C4001J or 128ms (MT4C4001J L) • Industry-standard pinout, timing, functions and packages • High-performance CMOS silicon-gate process

Contextual Info: IBM0164800B 8M x 8 DRAM Features • Low Power Dissipation - Active: 396m W /360m W max - Standby (LVTTL Inputs): 7.2m W (max) - Standby (LVCMOS Inputs): 720m W (max) • 8,388,608 word by 8 bit organization • Single 3.3 + 0.3V power supply • 8192 refresh cycles/128ms

B1115

Abstract: mt4c4001 MT4C4001JDJ-6 4c4001 MT4C4001J JCSR
Contextual Info: MICRON SEMICONDUCTOR INC b3E D • b l l l S 4 cì 0D07b2tì 4D2 BURN MT4C4001 J L 1 MEG X 4 DRAM M IC R O N DRAM 1 MEG x 4 DRAM DRAM STANDARD OR LOW POWER, EXTENDED REFRESH FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J L)

iocc

Contextual Info: 義隆電子股份有限公司 ELAN MICROELECTRONICS CORP. The application code of EEPROM writing. WRITE_EEPROM: BS 0x3,7 ;set control bank1 MOV A,@0x02 MOV RE,A ;EEPROM erase command MOV A,@ERASE_DELAY CALL DLAY_PAGE0 ;delay 128ms MOV A,@0x80 CALL DLAY_PAGE0

implement codec G.711

Contextual Info: CMOS MT9122 Dual Voice Echo Canceller Preliminary Information with Tone Detection Features • • • • • • • • • • • • • ISSUE 5 Dual channel 64ms or single channel 128ms echo cancellation Conforms to ITU-T G.165 requirements ITU-T G.165/G.164 disable tone detection