40LMB Search Results

c46cm

Abstract: CY7C460 CY7C462 CY7C464 IDT7205 IDT7206
Contextual Info: CY7C460 CY7C462 CY7C464 m .W C Y P R E S S C ascadable 8 K x 9 F I F O C ascadable 16K x 9 FIFO C ascadable 3 2 K x 9 FIFO Features • • • • • • • • • • • • • • • data outputs go to the high-impedance Functional Description state when R is H IG H .

CY7C225A

Contextual Info: CY7C225A '= C Y P R E S S Features • CMOS for optimum speed/power • High speed — 18 ns address set-up — 12 ns clock to output • Low power — 495 mW commercial — 660 mW (military) • Synchronous and asynchronous out­ put enables • On-chip edge-triggered registers

L496D

Abstract: 9l reset CY7C331 ST L11922 0423-J
Contextual Info: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

16L88

Abstract: PALC20 PALC16R6-20DMB cypress 16R4 PALC16L8-30DMB 16L8 16R4 16R6 16R8 PALC16R6-30DMB
Contextual Info: 256=^2 ooQb^o s d c y p MbE D CYPRESS SEMICONDUCTOR PAL C20 Series ~ SEMICONDUCTOR Features • CMOS EPROM technology for « p ro ­ grammability • High performance at quarter power • — tpo = 25 ns — ts = 20 ns — tco = 15 ns — Ice = 45 mA • High performance at military

Contextual Info: CY7C330 C Y P R E S S •0 Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers

Contextual Info: CY7C277 '# C Y P R E S S Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 30-ns address set-up — 15-ns dock to output • Low power — 660 mW commercial — 715 mW (military) • Programmable address latch enable

Contextual Info: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin

Contextual Info: CY7C909 CY7C911 CYPRESS SEMICONDUCTOR Features • Fast — CY7C909/11 has a 30-ns min. clock-to-output cycle time (com­ mercial and military) • Low power — Ic c (max.) = 55 mA (commercial and militaiy) • V cc margin — 5V+10% — All parameters guaranteed over

transistor c331

Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
Contextual Info: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the

CY7C429-25PC

Abstract: CY7C420 CY7C421 CY7C425 CY7C429 IDT7201 IDT7202 IDT7203 CY7C429-30DC vcy7
Contextual Info: bSE D • S S ö ^ b b E O O l O bB l bTD I CYPRESS SEMICONDUCTOR CYPRESS SEMICONDUCTOR ICYP CY7C420, CY7C421 CY7C424, CY7C425 CY7C428, CY7C429 Cascadable 512 x 9 FIFO Cascadable lK x 9 FIFO Cascadable 2K x 9 FIFO • TTL compatible • Three-state outputs

CY7c911

Abstract: CY7C909 stk 654 C909 CY7C911-30PC Register push pop
Contextual Info: CY7C909 CY7C911 CMOS Micro Program Sequencers CYPRESS SEMICONDUCTOR Features • Fast — CY7C909/11 has a 30-ns min. clock-to-output cycle time (com­ mercial and military) • Low power — Icc (max.) = 55 mA (commercial and military) • V<x' margin —5V+1»%

TCO - 909 F 10 MHz

Abstract: TCO - 909 C335 CY7C335 TCO - 909 F C335A
Contextual Info: CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer

CY7C419

Abstract: CY7C420 CY7C421 CY7C425 IDT7200 IDT7201 IDT7202 IDT7203 IDT7204 7C43
Contextual Info: fax id: 5404 /25/29/ CY7C419/21/25/29/33 256 x 9, 512 x 9, 1K x 9, 2K x 9, 4K x 9 Cascadable FIFO Features • 256 x 9, 512 x 9, 1,024 x 9, 2048 x 9, and 4096 x 9 FIFO buffer memory • Dual-port RAM cell • Asynchronous read/write • High-speed 50.0-MHz read/write independent of

Contextual Info: CY7C470 CY7C472 CY7C474 F/ C Y P R E S S 8K x 9 FIFO, 16Kx 9 FIFO, 32K x 9 FIFO with Programmable Flags Features Functional Description • 8K x 9 , 16K x 9, an d 32K x 9 FIFO buffer memory • A synchronous read/write • H igh-speed 33.3-M H z read/write

CY7C470

Abstract: CY7C472 CY7C474 pfr 4fi
Contextual Info: W CYPRESS CY7C470 CY7C472 CY7C474 8K x 9 FIFO, 16K x 9 FIFO, 32K x 9 FIFO with Programmable Flags Features Functional Description • 8K x 9 16K x 9, and 32K x 9 FIFO buffer memory • Asynchronous read/write • High-speed 333-M H z read/write independent of depth/width

B 503 Potentiometers

Abstract: cy7c421 COML-55 FF p21 CY7C419 IDT7200 IDT7201 IDT7202 IDT7203 IDT7204
Contextual Info: CY7C419/21/25/29/33 r* CYPRESS Features • 256 x 9, 512 x 9,1,024 x 9,2048 x 9, and 4096 x 9 FIFO buffer memory • Dual-port RAM cell • Asynchronous read/write • High-speed 50.0-MHz read/write independent o f depth/width • Low operating power — I c c i = 35 mA

TCO - 909 F 10 MHz

Abstract: TCO - 909 F CERAMIC LEADLESS CHIP CARRIER C335 CY7C335
Contextual Info: CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer

C3317

Abstract: L1190 CY7331
Contextual Info: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all

CY7C425-15JI

Abstract: 7C419
Contextual Info: 2 5 6 x 9 , 5 1 2 x 9 , 1K x 9, 2 K x 9 , 4 K x 9 C ascadable FIFO Features • 256 x 9,512 x 9,1,024 x 9,2048 x 9, and 4096 x 9 FIFO buffer memory • Dual-port RAM cell • Asynchronous read/write • High-speed 50.0-MHz read/write independent of depth/width

Contextual Info: i \j h ì v . I i/£ ty a u CY7C470 CY7C472 CY7C474 Revision: August 15f 1994 r # C Y PR ESS 8K x 9 FIFO, 16K x 9 FIFO, 32K x 9 FIFO with Programmable Flags Features • 8K x 9 ,16K x 9, and 32K x 9 FIFO • • • • • • • • • • • buffer memory

Contextual Info: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Generic architecture to replace stan­ dard logic functions including: 20L10, 20L8,20R8,20R6,20R4,12L10,14L8, 16L6,18L4,20L2, and 20V8 Eight product term s and one OE product term per output

Contextual Info: CY7C168 CY7C169 CYPRESS SEMICONDUCTOR Features Functional Description • Automatic power-down when dese­ lected 7C16S • CMOS for optimum speed/power • Highspeed — tAA = 25 ns — tACE = IS ns (7C169) • Low active power — 385 mW • Low standby power (7C168)

CY7C425

Abstract: CY7C420 CY7C429-30DC CY7C42I-25JI CY7C421-40DC CY7C421 CY7C429 IDT7201 IDT7203 CY7C429-30PC
Contextual Info: 4bE D CYPRESS SSflTbbS □007117 5 OCYP CY7C420, CY7C421 CY7C424, CY7C425 CY7C428* CY7C429 SEMICONDUCTOR CYPRESS SEMICONDUCTOR Cascadeable 512 x 9 FIFO Cascadeable IK x 9 FIFO Cascadeable 2K x 9 FIFO 'T - 'A W • TTL compatible • Three-state outputs • Pin compatible and functional

333Q

Abstract: CY7C439 tba9 DIAGRAM-12
Contextual Info: CYPRESS SEMI CONDUCTOR bSE D BSf i ^bbE OOlDbai 11b « C Y P CY7C439 CYPRESS SEMICONDUCTOR Bidirectional 2K x 9 FIFO Features Functional Description • 2048 x 9 FIFO butter memory • Bidirectional operation • High-speed 28.5-MHz asynchronous reads and writes