480FL Search Results

Contextual Info: MITSUBISHI LSIs •0 0 ^ M5M5V278DP,J,FP,VP-15 1994.02 Note*: This It not • firmi tpftddcaUon. loa^Bg» 262144-BIT 32768-WORD BY 8-BIT CMOS STA TIC RAM DESCRIPTION The M5M5V278D is a family of32768-word by 8-hit static RAMs, fabricated with the high-performance CMOS silicon gate MOS

Contextual Info: SN55116, SN75116, SN75118 DIFFERENTIAL LINE TRANSCEIVERS SLLS073C - MAY 1976 - REVISED MARCH 1997 features common to all types additional features of the SN55116/SN75116 • • • • Single 5-V Supply 3-State Driver Output Circuitry TTL-Compatible Driver Inputs

6001.005

Abstract: a724 64KX32 64KX4 DO001
Contextual Info: DENSE-PAC MICROSYSTEMS 07E D | 57Se 41S ODQaiMO O | 64KX4 BASED Dense-Pac Microsystems, Ine. CM O S SRAM FAMILY -7 = *ñ -¿> 3 -/Q y '- DESCRIPTION: The Dense-Pac 64KX4 Based Family consiste of static random acce ss m em ories SRA M S) organized as described below.

095 SONY

Contextual Info: CXK58258AP/AJ SONY. - 15/ 20/25 Preliminary 32,768-word x 8-bit High Speed CMOS Static RAM Description The C X K 58258A P /A J is a high speed CMOS static RAM which consists o f 32,768-word x 8-bit. It operates at 15 / 2 0 / 2 5 n s access time from 5V single power supply.

1VA120

Contextual Info: TOSHIBA MOS MEMORY PRODÜCTS TC55464P/J-20, TC55464P/J-25 TC55464P/J-35 ,_ , ID E S C R IP T IO N 1 The TC55464P/J is a 262,144 b i ts high speed s t a t i c random access memory organ ized as 65,536 words by 4 b i ts using CMOS tech n o lo g y , and operated from a s in g le 5 -v o lt supply.

Contextual Info: General-Purpose Interface Bus Transceiver t / • IR7C161A/IR7C162A - IR7C161A/IR7C162A General-Purpose Interface Bus Transceiver ■ Pin Connections Descriprtion IR7C161A T h e I R 7 C 16 1 A / I R 7 C 1 6 2 A is an 8-channel tra n s c e iv e r for G P IB general purpose interface

S7C1024-20TJC

Abstract: 7C1024
Contextual Info: Features • O rg a n iz a tio n : 1 3 1 ,0 7 2 w o r d s x 8 b its • T T L /L V T T L -com patible, th re e -s ta te I / O • H ig h s p e e d • 3 2 - p in JEDEC sta n d a rd p ackages - 3 0 0 m il PDIP a n d SOJ - 1 0 / 1 2 / 1 5 / 2 0 n s a d d re ss access tim e

Contextual Info: SHARP E L E K / MELEC D IV 1SE 0 | a iflQ ? ^ General-Purpose Interface Bus Transceiver O O O S ia t o | IR7C160A/IR7C163A "T'75'5i IR7C160A General-Purpose Interface Bus Transceiver IR7C163A General-Purpose Interface Bus Transceiver M eets IEEE standard 488-1978 GPIB

Contextual Info: L 7 C 1 9 4 /1 9 5 64K x 4 Static RAM D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES □ 64K x 4 Static RAM with Common I/O □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 15 ns maximum □ Low Power Operation Active: 210 mW typical at 35 ns

Contextual Info: Paradigm P D M 4 M 6 1 8 9 256 KByte Second Level Cache Modules for Intel Pentium CPUs Features Description 256 KByte asynchronous second level cache. L. Pin compatible with the PDM4M6181 /6182. J Ideal for use with Intel Pentium™ CPU based systems. Especially those using Intel's 82430NX