4M X 36 RAM Search Results

STI364000

Contextual Info: STI364000 72-PIN SIMMS 4M X 36 DRAM SIMM Memory Module FEATURES GENERAL DESCRIPTION • The Simple Technology STI364000 is a 4M bits x 36 Dynamic RAM high density memory module. The Simple Technology STI364000 consist of eight CMOS 4M x 4 DRAMs in 24-pin SOJ package and four CMOS 4M x 1 bit DRAMs in a 20-pin

Contextual Info: CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description • 36-Mbit Density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

Contextual Info: CY7C1417AV18 CY7C1419AV18 CY7C1421AV18 PRELIMINARY 36-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 The CY7C1417AV18, CY7C1428AV18, CY7C1419AV18, and CY7C1421AV18 are 1.8V Synchronous Pipelined SRAM

3M Touch Systems

Contextual Info: CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 36-Mbit Density (4M x 8, 4M x 9, 2M x 18, 1M x 36) ■ 450 MHz Clock for High Bandwidth ■

CY7C12481

Abstract: CY7C12501 3M Touch Systems
Contextual Info: CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 36-Mbit Density (4M x 8, 4M x 9, 2M x 18, 1M x 36) ■ 450 MHz Clock for High Bandwidth ■

CY7C12481

Contextual Info: CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 36-Mbit Density (4M x 8, 4M x 9, 2M x 18, 1M x 36) ■ 450 MHz Clock for High Bandwidth ■

KMM5364100-7

Abstract: Ras 1220
Contextual Info: DRAM MODULES KMM5364100/G 4M X 36 DRAM SIMM Memory Module FEATURES GENERAL DESCRIPTION • Performance range: The Samsung KMM5364100 is a 4M bit x 36 Dynamic RAM high density memory module. The Samsung KMM5364100 consist of eight CMOS 4M x 4 bit DRAMs in 24-pin SOJ packages and four CMOS 4 M x 1 bit

CY7C1246V18

Abstract: CY7C1248V18 CY7C1250V18 CY7C1257V18
Contextual Info: CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) ■ 300 MHz to 375 MHz clock for high bandwidth

CY7C1266V18

Abstract: CY7C1268V18 CY7C1270V18 CY7C1277V18
Contextual Info: CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) ■ 300 MHz to 400 MHz clock for high bandwidth

Contextual Info: CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 PRELIMINARY 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1266V18 CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • • • • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300 MHz to 400 MHz clock for high bandwidth

CY7C1416JV18

Abstract: CY7C1418JV18 CY7C1420JV18 CY7C1427JV18 MAX9930
Contextual Info: CY7C1416JV18, CY7C1427JV18 CY7C1418JV18, CY7C1420JV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

Contextual Info: CY7C1417AV18 CY7C1428AV18 CY7C1419AV18 CY7C1421AV18 PRELIMINARY 36-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency

CY7C1416AV18

Abstract: CY7C1418AV18 CY7C1420AV18 CY7C1427AV18
Contextual Info: CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

CY7C1422AV18

Abstract: CY7C1423AV18 CY7C1424AV18 CY7C1429AV18
Contextual Info: CY7C1422AV18, CY7C1429AV18 CY7C1423AV18, CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

CY7C1250V18-333BZC

Abstract: CY7C1246V18 CY7C1248V18 CY7C1250V18 CY7C1257V18
Contextual Info: CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • • • • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300 MHz to 375 MHz clock for high bandwidth

CY7C1416AV18

Abstract: CY7C1418AV18 CY7C1420AV18 CY7C1427AV18
Contextual Info: CY7C1416AV18 CY7C1427AV18 CY7C1418AV18 CY7C1420AV18 PRELIMINARY 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1422JV18, CY7C1429JV18 CY7C1423JV18, CY7C1424JV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36 Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

Contextual Info: CY7C14161KV18, CY7C14271KV18 CY7C14181KV18, CY7C14201KV18 36-Mbit DDR II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit Density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 333 MHz Clock for High Bandwidth ■ 2-word Burst for reducing Address Bus Frequency

CY7C1428AV18-250BZC

Contextual Info: CY7C1417AV18 CY7C1428AV18 CY7C1419AV18 CY7C1421AV18 36-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency

CY7C1416BV18

Abstract: CY7C1418BV18 CY7C1420BV18 CY7C1427BV18
Contextual Info: CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 PRELIMINARY 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1422AV18 CY7C1423AV18 CY7C1424AV18 PRELIMINARY 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C14161KV18, CY7C14271KV18 CY7C14181KV18, CY7C14201KV18 36-Mbit DDR II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit Density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 333 MHz Clock for High Bandwidth ■ 2-word Burst for reducing Address Bus Frequency