54LS113A Search Results

pr 5104

Abstract: UTRX
Contextual Info: ^ M O T O R O L A M ilitary 54LS 113A Dual J-K Flip-Flop W ith P reset MPO lllllll ELECTRICALLY TESTED PER: MIL-M-38510/30104 The 54LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH,

Contextual Info: M M O T O R O L A Military 54LS113A Dual J-K Flip-Flop With Preset M ELECTRICALLY TESTED PER: MIL-M-38510/30104 P O m in i T h e 5 4 L S 1 1 3 A o ffe r s in d iv id u a l J , K , s e t, a n d c lo c k in p u ts . T h e s e m o n o lith ic d u a l flip -flo p s a r e d e s ig n e d s o th a t w h e n th e c lo c k g o e s H I G H ,

motorola ic 6116

Contextual Info: M m o to r o la Military 54LS113A D u a l J -K Flip -Flo p W ith P re se t ELECTRICALLY TESTED PER: MIL-M-38510/30104 The 54LS113A o ffe rs in d ivid u a l J, K, set, and clock in p u ts. These m o n o lith ic dual flip -flo p s are designed so th a t w hen th e clock goes

SN54S113

Abstract: SN74LS113A SN54LS113A SN74 SN74S113A
Contextual Info: 54LS113A, SN54S113, SN74LS113A, SN74S113A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET D2661, APRIL 1982 - REVISED MARCH 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance SN 54LS113A . S N 54S 113 . . . J OR W PACKAGE SN 74LS 113A . S N 74S 113A . . . O OR N PACKAGE

S113

Abstract: SN54LS113A SN54S113 SN74 SN74LS113A SN74S112 SN74S113
Contextual Info: TYPES 54LS113A, SN54S113, SN74LS113A, SN74S113 DUAL J -K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET REVISED DECEMBER 1983 F u lly B u ffe re d to O ffe r M a x im u m Isola tio n fro m E xtern al D is tu rb a n c e S N 5 4 L S 1 1 3 A , S N 5 4 S 1 1 3 . . . J OR W PACKAG E

Contextual Info: M MOTOROLA M ilitary 5 4 LS 7 3 A Dual J-K Flip-Flop With Clear ELECTRICALLY TESTED PER: MIL-M-38510/30101 The 54LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that w hen the clock goes HIGH, the inputs are enabled and data will be accepted. The logic of the J and K inputs may

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

74s113a

Abstract: SN74LS113 74ls113a
Contextual Info: 54LS113A, SN54S113, SN74LS113A, SN74S113A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET D2661, APRIL 1982 - REVISEO MARCH 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance S N 5 4 L S 1 1 3 A , S N 5 4 S 1 1 3 . . . J OR W P A C K A G E

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

Contextual Info: M MOTOROLA M ilita ry 54L S 73A Dual J-K Flip-Flop W ith C lear ELECTRICALLY TESTED PER: MIL-M-38510/30101 M mini The 5 4 L S 7 3 A offers individual J, K, clear, and clock inputs. These dual flip -flo p s are desig n ed so th a t w hen the clo ck g oe s HIG H , th e inputs

Contextual Info: 54LS113A, SN54S113, SN74LS113A, SN74S113A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET D2661, APRIL 1982 - REVISED MARCH 1988 Fully Buffered to Offer Meximum Isolation from External Disturbance SNS4LS113A. SN54S113 . . . J OR W PACKAGE SN74LS113A. SN74S113A . . . O OR N PACKAGE

SN74LS113A

Contextual Info: TYPES 54LS113A, SN54S113, SN74LS113A, SN74S113 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET REVISED DECEMBER 1983 Fully Buffered to O ifer M axim um Isolation fro m External Disturbance S N 54LS 113A , S N 54S 113 . . . J OR W PACKAGE S N 74LS 113A , S N 74S 113 . . D , J OR N PACKAGE

DM54

Abstract: DM74 DM74LS113A FTHA
Contextual Info: 54LS113A/DM74LS113A National Semiconductor 54LS113A/DM74LS113A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Complementary Outputs General Description Absolute Maximum Ratings Note d T h is d e vice c o n ta in s tw o in d e p e n d e n t neg a tive -ed g e trig g e re d J-K flip -flo p s w ith c o m p le m e n ta ry o u tp u ts .

logos 4012B

Abstract: 1LB553 Rauland ETS-003 Silec Semiconductors MCP 7833 4057A transistor sr52 74c912 1TK552 74S485
Contextual Info: L p i > « , * S E m Ic O N VOLUM E 3 INTERNATIONAL INTEGRATED CIRCUITS INDEX 5th EDITION 1985 Revised June 1985 COMPILED AND PUBLISHED BY S E M IC O N IN D E X E S L IM IT E D THE SEMICON INDEX SERIES CONSISTS OF VOLUME 1 TRANSISTOR INDEX VOLUME 2 DIODE & SCR INDEX