54AC Search Results

Contextual Info: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise

2SC 2320

Abstract: SCAS04QA-P3110
Contextual Info: 54ACT11253,74ACT11253 DUAL 1-0F-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCAS040A - D3110, MARCH 1988 - REVISED APRIL 1993 * Inputs Are TTL-Voltage Compatible 54ACT11253 . . . J PACKAGE 74ACT11253 . . . D OH N PACKAGE TOP VIEW * 3-State Version of'ACT11153

Contextual Info: 54ACT11521, 74ACT11521 8-BIT IDENTITY COMPARATORS S C A S Q 2 3 A - D2957, JU L Y 1978- R E V IS E D A P R I L 1993 54ACT11521 . . . J P A C K A G E 74ACT11521 . . . OB, D W O R N P A C K A G E i * Compares Two 8-Bit Words * Inputs Are TTL-Voltage Compatible

Contextual Info: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise

1sv 134

Contextual Info: 54ACT11640, 74ACT11640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS027A - D2957, JULY 1987 - REVISED APRIL 1993 54ACT11640. . . JT PACKAGE 74ACT11640 . . . DW OR NT PACKAGE TOP VIEW B idirectional Bus Transceivers In H ig h-D ensity 24-P in Packages

74AC11827

Contextual Info: 54AC11827, 74AC11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS TI0155— 0 3 3 7 9 . NOVEMBER 1989— REVISED MARCH 1990 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 54AC11827 . . . JT PACKAGE 74AC11827 . . . DW OR NT PACKAGE TOP VIEW

D2957

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

74AC11520

Contextual Info: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations

2a117

Contextual Info: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to

Contextual Info: 54ACT11652, 74ACT11652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS TI0123— D3106, DECEMBER 1989 5 4 A C T 11 6 52 . . . J T PACKA GE • Inputs are TTL-Voltage Compatible 7 4 A C T 1 1652 . . . D W OR N T P ACKA G E • Bus Transceivers/Registers

Contextual Info: 54AC 11004, 74AC11004 HEX INVERTERS TI0044— D2957, FEBRUARY 1068— REVISED M ARCH 1990 54AC11004 . . . J PACKAGE 74AC11004 . . . DW OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin Vq c and GND Configurations to

Contextual Info: 54AC11377, 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE TI0180— D3420, M A R C H 1990 Contains Eight D-Type Flip-Flops 54AC11377 . . . JT PACKAGE 74AC11377 . . . DW OR NT PACKAGE Clock Enable Latched to Avoid False Clocking TOP VIEW 1Q [ 2Q [ 3Q [

TI0149-D3373

Contextual Info: 54ACT11827, 74ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS TI0149— D3373, NOVEM BER 19B9— REVISED MARCH 1990 54ACT11827 . . . JT PACKAGE 74ACT11827 . . . DW OR NT PACKAGE • Inputs are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer

54ACS

Abstract: LT26
Contextual Info: a d v a n c e in fo r m a t i o n \ J T 54ACS 193/54ACTS 193 Radiation-Hardened Synchronous 4-Bit Up-Down Counters FEATURES • • • • • • • • • • Look-ahead circuitry enhances cascaded counters Fully synchomous in count modes Parallel asynchronous load for modulo-N count lengths

tl401

Contextual Info: 54ACT11074, 74ACT11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCAS046 - D2957. DECEMBER 1986 - REVISED APRIL 1993 54ACT11074. . . J PACKAGE 74ACT11074. . . D OR N PACKAGE * Inputs Are TTL-Voltage Compatible

54AC11181

Abstract: TI018
Contextual Info: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T I0184— D 3119, APRIL 1989— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE TOP VIEW Minimize High-Speed Switching Noise

74AC11873

Contextual Info: 54AC11873, 74AC11873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS • 54A C 11 8 73 . . . J T P A C K A G E 3-State Buffer-Type Outputs Drive Bus 74AC 11B73 . . . D W OR N T P A C K A G E Lines Directly TOP V IE W • Bus-Structured Pinout • Flow -Through A rchitecture O ptim izes PCB

Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0053— D 2957, JUNE 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54ACT11020 . . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout

Contextual Info: 54ACT11241, 74ACT11241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS T I0073— D2957 JULY 1987— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54A C T 11241 . . . J T P ACKA G E 74A C T11 2 41 . . . D W OH N T P ACKA G E • 3-State Outputs Drive Bus Lines or Buffer

Contextual Info: 54ACT11874, 74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS D3447, MAR CH 1990-R E V IS E D O C TO BER 1990 54A C T 11 8 74 . . . J T P A C K A G E Inputs are TTL-Voltage C om patible 74A C T 11 8 74 . . . D W O R N T P A C K A G E

74AC11533

Abstract: 123D20
Contextual Info: *»4AP11*511 744011*511 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0085— D2957, JULY 1987— REVISED JAN U AR Y 1990 54AC11533 . . . JT PACKAGE 74AC11533 . . . DW OR NT PACKAGE • 8-Latches in a Single Package • 3-State Bus-Driving Inverting Outputs