572P Search Results

IS46TR

Abstract: IS43TR82560A DDR3 DRAM 2GB 128Mx16 96BALL FBGA "2Gb DDR3 SDRAM"
Contextual Info: IS43/46TR16128A/AL, IS43/46TR82560A/AL 256Mx8, 128Mx16 2Gb DDR3 SDRAM ADVANCED INFORMATION MAY 2012 FEATURES • Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V  Low Voltage L : VDD and VDDQ = 1.35V + 0.1V, -0.067V        

NT5CB64M16AP-CF

Abstract: nt5cb64m16 NT5CB64M16AP-CG NT5CB64M16AP nanya NT5CB64M16AP NT5CB64m NT5CB64M16AP-BE nt5cb64m16ap-dh MPR 20 20 CF RESISTOR NT5CB64M16AP-AC
Contextual Info: 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Feature  Write Leveling  1.5V ± 0.075V JEDEC Standard Power Supply  OCD Calibration  8 Internal memory banks (BA0- BA2)  Dynamic ODT (Rtt_Nom & Rtt_WR)  Differential clock input (CK, )

P86AD

Contextual Info: □ MN101D01F/G / Y MN101D01F / G / Y under development |Type 1 ROM (x8-bit) 9 6 K /1 2 8 K /1 2 8 K 1 RAM (x8-bit) 2560 / 3072 / 3072 1 Minimum Instruction Execution Time With Main Clock operated 0.1397 ps (at 4.0 lo 5.5V, 14.32MHz) When Sub-clock operated

Contextual Info: IS43/46TR16640A, IS43/46TR16640AL IS43/46TR81280A, IS43/46TR81280AL 128MX8, 64MX16 1Gb DDR3 SDRAM NOVEMBER 2013 FEATURES • Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V  Low Voltage L : VDD and VDDQ = 1.35V + 0.1V, -0.067V       

Contextual Info: IS43/46TR16128A, IS43/46TR16128AL, IS43/46TR82560A, IS43/46TR82560AL 256Mx8, 128Mx16 2Gb DDR3 SDRAM NOVEMBER 2013 FEATURES • Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V  Low Voltage L : VDD and VDDQ = 1.35V + 0.1V, -0.067V      

Contextual Info: IS43/46TR16640B, IS43/46TR16640BL IS43/46TR81280B, IS43/46TR81280BL 128MX8, 64MX16 1Gb DDR3 SDRAM NOVEMBER 2014 FEATURES • Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V  Low Voltage L : VDD and VDDQ = 1.35V + 0.1V, -0.067V  Refresh Interval: 7.8 us (8192 cycles/64 ms) Tc= -40°C to 85°C

AIIGX53001-3

Abstract: half bridge converter 2kw higig pause frame EP2AGX65 EP2AGX65DF29 HDTV transmitter receivers block diagram 32-Bit Parallel-IN Serial-OUT Shift Register prbs parity checker and generator SILICON General 741 PMD Motion
Contextual Info: Arria II GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-3.0 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

Contextual Info: SG572568FU8EWUU June 28, 2010 Ordering Information Part Numbers Description Module Speed SG572568FH8EWLC 256Mx72 2GB , DDR3, 204-pin Registered SO-RDIMM, Parity, ECC, 128Mx8 Based, DDR3-1066-777, 1.5V, 30.00mm, Green Module (RoHS Compliant). PC3-8500 @ CL 7, 8

Contextual Info: Arria II GX Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-2.0 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

EP2AGX260EF

Abstract: "switch power supply" handbook
Contextual Info: Arria II GX Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-1.1 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

Contextual Info: DATA SHEET 1G bits DDR3 SDRAM EDJ1108BABG 128M words x 8 bits EDJ1116BABG (64M words × 16 bits) Specifications Features • Density: 1G bits Organization  16M words × 8 bits × 8 banks (EDJ1108BABG)  8M words × 16 bits × 8 banks (EDJ1116BABG)

Contextual Info: IS43/46TR16256A, IS43/46TR16256AL, IS43/46TR85120A, IS43/46TR85120AL 512Mx8, 256Mx16 4Gb DDR3 SDRAM ADVANCED INFORMATION DECEMBER 2012 FEATURES • Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V • Low Voltage L : VDD and VDDQ = 1.35V + 0.1V, -0.067V •

NT5CB128M8CN

Abstract: NT5CB256M4CN NT5CB128
Contextual Info: 1Gb DDR3 SDRAM C-Die NT5CB256M4CN / NT5CB128M8CN Feature  1.5V ± 0.075V JEDEC Standard Power Supply  Write Leveling  8 Internal memory banks (BA0- BA2)  OCD Calibration  Differential clock input (CK, )  Dynamic ODT (Rtt_Nom & Rtt_WR)

NT5CB256M8DN

Abstract: NT5CB256m tl 555 c "2Gb DDR3 SDRAM" NT5CB256M8 NT5CB256 NT5CC256M8 NT5CC256
Contextual Info: 2Gb DDR3 SDRAM D-Die NT5CB512M4DN / NT5CB256M8DN NT5CC512M4DN / NT5CC256M8DN Feature  1.5V ± 0.075V / 1.35V -0.0675V/+0.1V JEDEC Standard Power Supply  Output Driver Impedance Control  Write Leveling  OCD Calibration  Dynamic ODT (Rtt_Nom & Rtt_WR)

EDJ4208BASE-DJ-F

Abstract: EDJ4208BASE EDJ4208BASE-GN-F 1024M ELPIDA DDR3 User
Contextual Info: DATA SHEET 4G bits DDR3 SDRAM EDJ4204BASE 1024M words x 4 bits EDJ4208BASE (512M words × 8 bits) Specifications Features • Density: 4G bits • Organization  128M words × 4 bits × 8 banks (EDJ4204BASE)  64M words × 8 bits × 8 banks (EDJ4208BASE)

IS43TR16640A

Contextual Info: IS43/46TR16640A, IS43/46TR16640AL IS43/46TR81280A , IS43/46TR81280AL 128MX8, 64MX16 1Gb DDR3 SDRAM ADVANCED INFORMATION NOVEMBER 2012 FEATURES • Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V • Low Voltage L : VDD and VDDQ = 1.35V + 0.1V, -0.067V •

EDJ4208EASE-DJ

Abstract: EDJ4208EASE-DJ-F 1024M DDR3 4G SPD DDR3L-1066F DDR3L-1333
Contextual Info: DATA SHEET 4G bits DDR3L SDRAM EDJ4204EASE 1024M words x 4 bits EDJ4208EASE (512M words × 8 bits) Specifications Features • Density: 4G bits • Organization  128M words × 4 bits × 8 banks (EDJ4204EASE)  64M words × 8 bits × 8 banks (EDJ4208EASE)

EP4CE6 package

Abstract: EP4CE40 Altera EP4CE6 EP4CE55 5M240Z 5M1270Z QFN148 5m570z 5M40 5M80
Contextual Info: Package Information Datasheet for Altera Devices DS-PKG-16.3 This datasheet provides package and thermal resistance information for Altera devices. Package information includes the ordering code reference, package acronym, leadframe material, lead finish plating , JEDEC outline reference, lead

EDJ4216BASE

Abstract: E1646E41 105WR
Contextual Info: DATA SHEET 4G bits DDR3 SDRAM EDJ4216BASE 256M words x 16 bits Specifications Features • Density: 4G bits • Organization: 32M words × 16 bits × 8 banks • Package: 96-ball FBGA ⎯ Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.5V ± 0.075V

EDJ2104EDBG

Abstract: ELPIDA DDR3 DDR3L-1066 edj2108EDBG E1797E41 EDJ2108EDBG-DJ-F EDJ2108EDBG-GN-F
Contextual Info: DATA SHEET 2G bits DDR3L SDRAM EDJ2104EDBG 512M words x 4 bits EDJ2108EDBG (256M words × 8 bits) Specifications Features • Density: 2G bits • Organization  64M words × 4 bits × 8 banks (EDJ2104EDBG)  32M words × 8 bits × 8 banks (EDJ2108EDBG)

J1108

Contextual Info: PRELIMINARY DATA SHEET 1G bits DDR3 SDRAM EDJ1108BABG 128M words x 8 bits EDJ1116BABG (64M words × 16 bits) Specifications Features • Density: 1G bits Organization  16M words × 8 bits × 8 banks (EDJ1108BABG)  8M words × 16 bits × 8 banks (EDJ1116BABG)

E1629E20

Abstract: EDJ1108BFBG-DJ-F
Contextual Info: PRELIMINARY DATA SHEET 1G bits DDR3 SDRAM EDJ1104BFBG 256M words x 4 bits EDJ1108BFBG (128M words × 8 bits) Specifications Features • Density: 1G bits • Organization ⎯ 32M words × 4 bits × 8 banks (EDJ1104BFBG) ⎯ 16M words × 8 bits × 8 banks (EDJ1108BFBG)

EDJ8216B5MB

Abstract: E1824E
Contextual Info: PRELIMINARY DATA SHEET 8G bits DDR3L SDRAM, DDP EDJ8216E5MB 512M words x 16 bits Specifications Features • Density: 8G bits • Organization  64M words × 16 bits × 8 banks • Package  96-ball FBGA  DDP: 2 pieces of 4G bits chip sealed in one

A1A4M

Abstract: ELPIDA DDR3 User
Contextual Info: DATA SHEET 1G bits DDR3 SDRAM EDJ1108BABG 128M words x 8 bits EDJ1116BABG (64M words × 16 bits) Features • Density: 1G bits Organization  16M words × 8 bits × 8 banks (EDJ1108BABG)  8M words × 16 bits × 8 banks (EDJ1116BABG) • Package  78-ball FBGA (EDJ1108BABG)