6TBL723 Search Results

t742

Contextual Info: SN54F621, SN74F621 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS SDFS004B - D2932, MARCH 1987 - REVISED OCTOBER 1993 • Local Bus-Latch Capability • Noninverting Logic • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic

Contextual Info: SN74BCT29853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SCBS002D - SEPTEMBER 1987 - REVISED APRIL 1994 DW OR NT PACKAGE TOP VIEW BiCMOS Process With TTL Inputs and Outputs State-of-the-Art BiCMOS Design Significantly Reduces Standby Current OEA[ A1[ A2[ A3 [

4AC17

Abstract: texas instruments fifo cascaded SN74ACT7808
Contextual Info: SN74ACT7808 2048 x 9 STROBED FIRST-IN, FIRST-OUT MEMORY _SCAS205B - FEBRUARY 1991 - REVISED SEPTEMBER 1995 Load Clocks and Unload Clocks Can Be Asynchronous or Coincident * 2048 Words by 9 Bits • Expansion Logic for Depth Cascading 9 Empty, Full, and Half-Full Flags

SN54LVT16952

Abstract: LVT16952 SN74LVT16952
Contextual Info: SN54LVT16952, SN74LVT16952 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS _ SCBS151A - MAY 1992 - REVISED JANUARY 1994 State-of-the-Art Advanced BiCMOS Technology ABT Design for 3.3-V Operation and Low-Static Power

SN54LVT16373

Abstract: LVT16373 hl723 SN74LVT16373
Contextual Info: SN54LVT16373, SN74LVT16373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS _ State-of-the-Art Advanced BiCMOS Technology ABT Design for 3.3-V Operation and Low-Static Power Dissipation Members of the Texas Instruments Widebus Family

74ACT11657

Contextual Info: _ 74ACT11657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS AUGUST 1992-R EVISED APRIL 1993 Inputs Are TTL-Voltage Compatible DW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout P A R IT Y [ 1 Center-Pin V c c and GND Pin

SN54ABT16640

Abstract: SN74ABT16640
Contextual Info: SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107B - APRIL 1992 - REVISED JULY 1994 SN54ABT16640. . . WD PACKAGE SN74ABT16 6 4 0 . DL PACKAGE TOP VIEW Members of the Texas Instruments Wldebus Family State-of-the-Art EPIC-UB™ BICMOS Design

Contextual Info: SN54LVTH18516, SN54LVTH182516, SN74LVTH18516, SN74LVTH182516 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS672A - AUGUST 1 9 9 6 - REVISED DECEMBER 1996 Members of the Texas Instruments SCOPE Family of Testability Products Members of the Texas Instruments

SN74BCT25240

Contextual Info: TEXAS INSTR LOGIC b3E D • 0 ^ 1 7 2 3 DD'ISMTS 3flb « T I I B SN54BCT25240, SN74BCT25240 25-OHM BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS101-D3532, JUNE 1990-REVISED JANUARY 1992 SN54BCT25240. . . JT PACKAGE SN74BCT25240 . . . DW OR NT PACKAGE • State-of-the-Art BiCMOS Design

Contextual Info: SN54F244, SN74F244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SDFS063A - D2932, MARCH 1987 - REVISED OCTOBER 1993 SN54F244 . . . J PACKAGE SN74F244 . . . DB, DW, OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Package Options Include Plastic

Contextual Info: SN74ALS620A, SN74ALS621A, SN74ALS623A, SN74AS623 OCTAL BUS TRANSCEIVERS S D A S 226A - DECEMBER 1982 - REVISED JANUARY 1995 • • Local Bus-Latch Capability ■ • Choice of True or Inverting Logic I I f • Package Options Include Plastic Small-Outline DW Packages and Standard

PRIORITY ENCODERS

Abstract: SCLS109 HC148 SN54HC148 SN74HC148 combinational logic circuit
Contextual Info: SN54HC148, SN74HC148 8-LINE TO 3-LINE PRIORITY ENCODERS _ S C LS 109C -M A R C H 1984 - REVISED JULY 1996 Encode Eight Data Lines to 3-Line Binary Octal Applications Include: - n-Bit Encoding - Code Converters and Generators Package Options Include Plastic

BO 817

Abstract: 5962-9470401QXA SN54ABT7819 010331A
Contextual Info: SN54ABT7819 512 x 18 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS305B - A UG U S T 1994 - REVISED D EC E M B ER 1995 • Member of the Texas Instruments Widebus Family • Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • Read and Write Operations Synchronized

SN74LV164

Contextual Info: SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER SCLS191 A - FEBRUARY 1 9 9 3 - REVISED JULY 1995 • EPIC Enhanced-Performance Implanted CMOS 2-|x Process • Typical Vq lp (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C • Typical Vq h v (Output Vqh Undershoot)

CDC391

Contextual Info: CDC391 M IN E TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS S C A S 3 3 4 A - D E CEM B ER 1992 - R EVISED N O V EM B E R 1995 Low Output Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs

FZK 105

Abstract: D1034A Z22V SN74ABT3614 fzk 101
Contextual Info: SN74ABT3614 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SCBS126F - JUNE 1992 - REVISED FEBRUARY 1996 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 x 36 Clocked FIFOs Buffering Data in Opposite Directions

Contextual Info: S N S A F *? ^N 74F 19 QUADRUPLE 2-INPUT POSITIVE-OR GATES SDFS044A- MARCH 1987 - REVISED OCTOBER 1993 SN54F32 . . . J PACKAGE SN74F32 . . . D OR N PACKAGE TOP VIEW Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic

w81b

Contextual Info: SN54ALS251, SN74ALS251 1-0F-8 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS S D A S 2 1 5 A -A P R IL 1982 - R E VIS ED D ECEM B ER 1994 SN54ALS251 . . . J PACKAGE SN74ALS251 . . . D OR N PACKAGE