74174 EQUIVALENT Search Results

74174 equivalent

Abstract: 74174 n74174 LS174 signetics
Contextual Info: S i g n e t i c 74174, LS174, S 174 Flip-Flops s Hex D Flip-Flops Product Specification Logic Products FEATURES • Six edge-triggered D-type flipflops • Three speed-power ranges available • Buffered common clock • Buffered, asynchronous Master Reset

74174 equivalent

Abstract: 74174 LS174 signetics
Contextual Info: 74174, LS174, S174 S ig n e f ic s Flip-Flops Hex D Flip-Flops Product Specification Logic Products FEATURES • Six edge-triggered O-type flipflops • Three speed-power ranges available • Buffered common clock • Buffered, asynchronous Master Reset TYPICAL f „ AX

D flip-flop 74175 pin data sheet

Abstract: IC 74175 SN74175N quad D flip-flop 74175 pin data sheet 7400 fan-out 7400 signetics 74175 pin data sheet quad D flip-flop 74175 pin 74174 data sheet IC 7400
Contextual Info: o ii5 S ,9 Am54/74174* Am54/74175 H ex/Q uadruple D-Type Flip-Flops with C lear Distinctive Characteristics \ Buffered clock and direct clear inputs. • • i Individual data input to each flip-flop. 35 M H z ty p ic a l c lo c k frequency. 100% r e lia b ility assurance testincj in com p lia n ce w ith

74174

Abstract: ttl 74174 74LS 74LS174 74S174 N74174N N74LS174D N74LS174N N74S174D N74S174N
Contextual Info: Signetics 7 4 1 7 4 , LS174 , S 174 Flip-Flops Hex D Flip-Flops Product Specification Logic Products FEATURES • Six edge-triggered D-type flip­ flops • Three speed-power ranges available • Buffered common clock • Buffered, asynchronous Master Reset

Contextual Info: R&E INTERNATIONAL, INC. 4174B CMOS HEX TYPE D FLIP-FLOP FEATURES: C O N N E C T IO N D IA G R A M • ■ ■ ■ ■ Static Operation All Inputs and Outputs Buffered Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Output Compatible with Two HTL Loads,

mc14174b

Abstract: ttl 74174 MC14174BCP 74174 equivalent
Contextual Info: MC14174B Hex Type D Flip-Flop The MC14174B hex type D flip–flop is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Data on the D inputs which meets the setup time requirements is transferred to the Q outputs on the positive edge of the

74171

Abstract: 7478 J-K Flip-Flop 7478 jk 74594 7400 series logic ICs shift register by using D flip-flop 7474 7498 4 bit 74395 74822 74278
Contextual Info: QAN1 Registers and Latches in the pASIC Architecture INTRODUCTION Quicklogic’s pASICTM 1 Family of high-performance FPGAs allows logic function speeds of over 100 MHz. The prime objective of the QuickLogic pASIC 1 Family logic cell is to maximize in-system device speed, while

74174 equivalent

Abstract: 14174B/BEAJC 14174B/BEAJC/883
Contextual Info: MC14174B Hex Type D Flip−Flop The MC14174B hex type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Data on the D inputs which meets the setup time requirements is transferred to the Q outputs on the positive edge of the

14174BG

Abstract: MC14174BCPG MC14174B MC14174BCP MC14174BD MC14174BDR2 MC14174BDR2G 74174 equivalent
Contextual Info: MC14174B Hex Type D Flip−Flop The MC14174B hex type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Data on the D inputs which meets the setup time requirements is transferred to the Q outputs on the positive edge of the

7408 CMOS

Abstract: TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 74106 CMOS 4017 series ttl 74395
Contextual Info: KG10000 SERIES SEMI-CUSTOM CMOS GATE ARRAY CMOS SILOCON GATE ARRAY Th e KG10000 S e rie s is c o n sists o f s ilico n gate C M O S arrays w hose inte rco n n e ctio n are in itia lly u n s p e c ifie d , th e re fo re custom LSI is p ro ce sse d w ith o n ly one m ask ste p a cu sto m ize d m etal m ask a c c o rd ­

Contextual Info: MC14174B Hex Type D Flip-Flop The MC14174B hex type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Data on the D inputs which meets the setup time requirements is transferred to the Q outputs on the positive edge of the

14174BG

Contextual Info: MC14174B Hex Type D Flip-Flop The MC14174B hex type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Data on the D inputs which meets the setup time requirements is transferred to the Q outputs on the positive edge of the

MC14174

Abstract: mc1417 MC14174BCPG
Contextual Info: MC14174B Hex Type D Flip-Flop The MC14174B hex type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Data on the D inputs which meets the setup time requirements is transferred to the Q outputs on the positive edge of the

TTL 74139

Abstract: 74153 mux MSI 74148 16cudslr CI 74138 sn 74373 8mcomp 7404 7408 7432 7408, 7404, 7486, 7432 Flip-Flop 7471
Contextual Info: PLSLIB-TTL /$ ^ n^ X LIBRARY • TTL MacroFunction Library Diskette. • ADLIB, Altera Design Librarian Diskette. To increase design ease and productivity Altera has created M acroFunctions. These are high level building blocks that allow the user to design at

14174B

Abstract: MC14174B MC14174BCP MC14174BD MC14174BDR2 MC14174BF MC14174BFEL
Contextual Info: MC14174B Hex Type D Flip−Flop The MC14174B hex type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Data on the D inputs which meets the setup time requirements is transferred to the Q outputs on the positive edge of the

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411
Contextual Info: P L S -W S /H P MAX+PLUS II Programmable Logic Software for HP/Apollo Workstations Data Sheet September 1991, ver. 3 Features □ □ LI LI □ □ □ □ General Description Software support for Classic, M A X 5000, M A X 7000, and ST G E P L D s Runs on H ew lett Packard /A p o llo Series 3000, 3500, 4000, 4500, and

MC14174

Abstract: mc14174bcp 14174B MC14174B MC14174BD MC14174BDR2 MC14174BF MC14174BFEL
Contextual Info: MC14174B Hex Type D Flip-Flop The MC14174B hex type D flip–flop is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Data on the D inputs which meets the setup time requirements is transferred to the Q outputs on the positive edge of the

14174B

Abstract: MC14174B MC14174BCP MC14174BD MC14174BDR2 MC14174BF MC14174BFEL
Contextual Info: MC14174B Hex Type D Flip-Flop The MC14174B hex type D flip–flop is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Data on the D inputs which meets the setup time requirements is transferred to the Q outputs on the positive edge of the

Contextual Info: MC14174B M O T O R O L A H E X TYPE D FLIP-FLOP L SUFFIX C ER AM IC C A S E 620 The MC14174B hex type 0 flip-flop is constructed with MOS Pchannel and N-channel enhancement mode devices in a single mono­ lithic structure. Data on the D inputs which meets the setup time

Contextual Info: MOTOROLA MC14174B H EX TYPE D FLIP-FLOP L SU F FIX C ER AM IC C A S E 620 The M C14174B hex type 0 flip-flop is constructed w ith MOS Pchannel and N-channel enhancement mode devices in a single mono­ lithic structure. Data on the D inputs w hich meets the setup time

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

TELEDYNE PHILBRICK OP AMP

Contextual Info: • W T E L E E Y N E PH ILBRIC K High Speed High Reliability Hybrid Deglitcher 4902 The 4902 high reliability hybrid deglitcher is designed to suppress transients at the output of digital to analog con­ verters. These transients or glitches occur at the output

ic 74226

Abstract: jk flip flop 74103 ic D flip flop 7474 7471 rs flip flop 4011 flip flop IC 7400 SERIES list Ic ttl 7490, 7493, 7495 ci 74386 7414 NOT gate ic IC LA 74141
Contextual Info: 1SE D RICOH CORP/ ELECTRONIC 7 7 4 4bTO 0G0Q7Qt, b RICOH No. 84-01 4-1-1984 Microelectronic Specification T -tfZ -3 1 RP3G01 0 2 • A N A L O G /D IG IT A L B I- C M O S GATE ARRAYS EFFICIENCY GENERAL DESCRIPTIO N T h e R P 3 G 01 and R P 3 G 0 2 a r e A n a lo g /D ig ita l

sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
Contextual Info: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher