74ALS645A Search Results

Contextual Info: M IT S U B IS H I ALSTTLs ? v ^> . 0 0 M 7 4 A L S 6 4 5 A - 1 P O C T A L B U S T R A N S C E IV E R W IT H 3 -S T A T E O U T P U T N O N IN V E R T E D 6249827 MITSUBTSHI 1 —- . CDOfT~LOGrc7 DESCRIPTION The M 74ALS645A-1P is a semiconductor integrated cir­

74ALS645AN

Abstract: 74ALS 74ALS645A 74ALS645A-1 74ALS645AD DIP20 SC603
Contextual Info: Philips Sem iconductors Product specification Octal transceiver 3-State 74ALS645A/74ALS645A-1 PIN CONFIGURATION FEATURES • Octal bidirectional bus interface 20] V qq T/R | T • 3-State buffer outputs sink 24m A and source 15mA 31 ÖE 3U B0 A0 U • Outputs are placed in high im pedance state during power-off

1e1l

Abstract: 74ALS 74ALS645A 74ALS645A-1 N74ALS645AD N74ALS645AN
Contextual Info: 74ALS645A, 74ALS645A-1 Transceivers Octal Transceivers 3-State FEATURES • Octal bidirectional bus interface • 3-state buffer outputs sink 24mA and source 15mA. ' • Outputs are placed In high imped­ ance state during power-off conditions • The -1 version sinks 48mA lOL

MS-012-AB

Abstract: 74ALS 74ALS645A 74ALS645A-1 N74ALS645AD N74ALS645AN TEXTOOL zif TEXTOOL zif 40 pin socket diode a7 SMAJ
Contextual Info: 74ALS645A, 74ALS645A-1 Signetics Transceivers Octal Transceivers 3-State Product Specification ALS Products FEATURES TYPE • Octal bidirectional bus interface • 3-state buffer outputs sink 24mA and source 15mA. • Outputs are placed in high imped­

744ALS645A-1D

Abstract: 74ALS 74ALS645A 74ALS645A-1 74ALS645A-1N 74ALS645AD 74ALS645AN
Contextual Info: INTEGRATED CIRCUITS 74ALS645A/74ALS645A–1 Octal transceiver 3–State Product specification IC05 Data Handbook Philips Semiconductors 1991 Jun 03 Philips Semiconductors Product specification Octal transceiver (3-State) 74ALS645A/74ALS645A-1 FEATURES PIN CONFIGURATION

Contextual Info: Philips Semiconductors Product specification Octal transceiver 3-State 74ALS645A/74ALS645A-1 FEATURES PIN CONFIGURATION • Octal bidirectional bus interface T/R • 3-State buffer outputs sink 24mA and source 15mA [I 20] VCC A0 H • Outputs are placed in high impedance state during power-off

Contextual Info: SN54ALS645A, SN54AS645, 74ALS645A, SN74AS645 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS S D A S278 - JA N U A R Y 1995 Bidirectional Bus Transceivers in High-Density 20-Pin Packages True Logic 3-State Outputs SN54ALS645A, SN54AS645 . . . J PACKAGE 74ALS645A, SN74AS645 . . . DW OR N PACKAGE

EATON CM20A

Abstract: A5 GNE mosfet Hall sensor 44e 402 2N8491 FTG 1087 S TRIAC BCR 10km FEB3T smd transistor marking 352a sharp EIA 577 sharp color tv schematic diagram MP-130 M mh-ce 10268
Contextual Info: Table of Contents N E W A R K E L E C T R O N IC S “Where serving you begins even before you call” Newark Electronics is a UNIQUE broadline distributor of electronic components, dedicated to provid­ ing complete service, fast delivery and in-depth inventory. Our main

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1035P TËJ MITSUB ISH I {DGTL LOGIC} Q012732 G | HEX NONINVERTING BUFFER W ITH OPEN COLLECTOR OUTPUT / DESCRIPTION PIN CONFIGURATION TOP VIEW ” T h e M 7 4 A L S 1 0 3 5 P is a s e m ic o n d u c to r in te g ra te d c ir­ c u it c o n s is tin g o f six n o n -inverting b u ffe rs w ith open

ci la 7610

Contextual Info: c +e MITSUBISHI ALSTTLs . op,00° M 74A L S 620A -1P v ie N v t ^s ^ - 3 _ OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI CDGTL LOGIC) DESCRIPTION The M74ALS6Í20A-1P is a semiconductor integrated cir­ cuit consisting of eight bus transm itter/receiver circuits

ci la 7610

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A LS 6 5 1 P 7 -52-3/ OCTAL BUS TRANSCEIVER/REGISTER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI 91 D 12674 (DGTL LOGIC ) DESCRIPTION The M74ALS651P is a semiconductor integrated circuit consisting of eight bus transceiver/registers with 3-state

Contextual Info: MITSUBISHI íDGTL LOGICI TI DEI't.E4*1ñ27 D0ia3flD S MITSUBISHI ALSTTLs M 624 9 82 7 M IT S U B IS H I DG TL L O G IC 7 4 A 91D L S 1 1 3 A P 12380 D DUAL J-K N EG A TIVE EDGE-TRIGGERED FLIP -FLO P W IT H SET T -H (* -o 7 -o y DESCRIPTION PIN CONFIGURATION (TOP VIEW)

m74als191p

Contextual Info: ÍDGTL LOGIC} 91D TI De | 12446 b241fl27 □ 0 1 2 4 4b ñ r D MITSUBISHI ALSTTLs M 74A LS191P SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER W ITH MODE CONTROL • 7 ^ V ' 5 ' ' ^ >3 DESCRIPTION - o 7 PIN CONFIGURATION TOP VIEW Th e M 7 4 A L S 1 9 1 P is a s e m ic o n d u c to r in te g ra te d c irc u it

74ALS640

Contextual Info: MITSUBISHI -CDGTL LOGIC} dT | ba^flS? D O i a k b B 4 M ITSUBISHI A L ST T Ls sc* -s s 5 " : . M 7 4 A LS6 4 7 P ,o.9B OCTAL BUS TR A N SC EIV ER /R EG IST ER WITH OPEN COLLECTOR OUTPUT NONINVERTED 6249827 MITSUBISHI CDGTL LOGTC) DESCRIPTION The M74ALS647P is a semiconductor integrated circuit

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A L S 1 0 0 2 À P a D eE| tk24=]aS7 0015712 > | MITSUBISHI IDGTL LOGIC} 11 QUADRUPLE 2-IN P U T PO SITIVE NOR BUFFER 7 ^ V 3 - /S DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M74ALS1002AP is a semiconductor integrated cir­ cuit consisting of four 2-input positive-logic NOR buffer

J 5027 R

Abstract: BEM 6K
Contextual Info: MIT SUBISH I íDGTL L O G I C } T I d ËT| ^5^027 ~JZ.SZt~3/ G0127SS □ MITSUBISHI ALSTTLs M 74A L S 1621A P I 62 49 8 2 7 M I T S U B I S H T T D G T L T o G r ^ ~ 910 12755 D OCTAL BUS TRANSCEIVER W ITH OPEN COLLECTOR OUTPUT NONINVERTED) DESCRIPTION

Contextual Info: MITSUBISHI -CDGTL L O G I O TI DE | bSMTfla? 001E4b4 □ M IT SU B ISH I ALSTTLs M74ALS241AP 6249827 MITSUBISHI DGTL LOGIC 91D 12464 D O CTAL B U F F E R /L IN E D R IV E R W IT H 3 -ST A T E O U T PU T (N O N IN V E R T E D ) DESCR IPTIO N The M74ALS241AP is a semiconductor integrated circuit

Contextual Info: MITSUBISHI ALSTTLs & M74ALS169BP T ' - v ’S '- J J - o SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER 6249827 MITSUBISHI DG TL LOGIC DESCRIPTION Th e M 74A L S 169 B P is a sem iconductor integrated circuit of a synchronous p resettable u p /d o w n

74als561

Contextual Info: MITSUBISHI íDGTL LOGIC} "DÌI bSMTñE? 00123ki7 5 TI W~ M IT S U B IS H I* !L. S T T L s M74ALS38AP 91D 12367 D 6249827 MITSUBISHI DGTL LOGIC QUADRUPLE 2 -IN P U T P O S ITIV E NAND BUFFER W IT H OPEN COLLECTOR OU TPUT T - - V 3 - / S DESCRIPTION PIN CONFIGURATION (TOP VIEW)

Contextual Info: "d ë J M ITS UBISHI -CDGTL L O G I O bEMTfla? ooiBS'in a S^Ls MITSUBISHI ALSTTLs M 74ALS133P r _ 6249827 MITSUBISHI - y j - / r SINGLE 13-IN PU T POSITIVE NAND GATE DGTL LOGIC DESCRIPTION Th e M 7 4A LS 133P is a sem iconductor integrated circuit

m74als

Abstract: M74ALS109AP 74ALS640
Contextual Info: M IT S U B IS H I {D G T l T o G IcT ^ I b H 1 SS? M 6249827 MITSUBISHI 7 4 A CDGTL LOGIC 91D J STTLs L S 1 0 9 A 12 37 4 P D DUAL J-R POSITIVE EDGE-TRIGGERED FLIP-FLOP W ITH SET AND RESET T -V & -0 7 - Ô ? DESCRIPTION PIN CONFIGURATION TOP VIEW) The M74ALS109AP is a semiconductor Integrated circuit

gt 568

Abstract: m74als568ap m74als568a
Contextual Info: MITSUBISHI -CDGTL L O G I O de! TI tsMiaa? QGiasai 4 |~~ M IT S U B IS H I ALSTTLs ~ J- M 74A LS 568A P S Y N C H R O N O U S P R E S E T T A B L E U P /O O W N D EC A D E C O U N TE R _ W IT H 3 -S T A T E O U T P U T 1H249827 MITSIJBISHI

M74ALS1032AP

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1 0 3 2 AP M I T S U B I S H I - C D G T L L O G I C } T I D È I ” L ^ M ^ ñ S ? 1 2 7 5 fi QUADRUPLE 2-IN P U T POSITIVE OR BUFFER _ DESCRIPTION _ _ _ _ PIN CONFIGURATION TOP VIEW The M74ALS1032AP is a semiconductor integrated cir­

Philips Semiconductors Selection Guide

Abstract: 74ALS08
Contextual Info: Philips Semiconductors Functional selection guide GATES FUNCTION INVERTERS NAND NOR DEVICE NUMBER NUMBER OF PINS Hex inverters 74ALS04B 14 Quad 2-input 74ALS00A 14 Triple 3-input 74ALS10A 14 Dual 4-input 74ALS20A 14 8-input 74ALS30A 14 Quint 2-input NAND, open collector