74LS74A IC Search Results

74ls74a

Abstract: 751A-02
Contextual Info: SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.

74LS74A

Abstract: 751A-02
Contextual Info: SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.

Contextual Info: GD54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERD FLIP-FLOPS WITH PRESET AND CLEAR Description This device contains two independent D-type positive edge triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the

74LS74A

Abstract: 54LS 74LS
Contextual Info: GD54/74LS74A DUAL D-TYPE POS.T.VE EDGE-TRIGGED FLIP-FLOPS Description Pin Configuration This device contains tw o ind epen den t D -typ e positive ed g e triggered flip-flops. A low level at the p reset or clear inputs sets or resets the outputs regardless of the levels of the

74LS74A

Contextual Info: <g> MOTOROLA SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The S N 54/74LS 74A dual edge-triggered flip-flop utilizes Schottky TTL cir­ cuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also com plementary Q and Q outputs.

74LS74A

Contextual Info: M M O T O R O L A SN54/74LS74A D E S C R I P T I O N - The S N 5 4 L S /7 4 L S 7 4 A dual edge-triggered flip-flop u tilizes Schottky TTL circu itry to produce high speed D-type flip-flops. Each flip-flop has individual cfear and set inputs, arid also com plem entary

Contextual Info: H D 74LS74A . Dual D-type Positive Edge-triggered Flip-Flops with Preset and Clear • P IN ARRANGEMENT ■FU N C T IO N TABLE O utputs Inputs P re s e t C lear Clock D Q Q L H X X H L H L X X L H L L X X H* H* H H H H L H H L L H H H X Qo Qo L Notes) H; high level, L; low level, X; irrelevant

74LS74AN

Contextual Info: S E M IC O N D U C T O R tm hold tim es are not violated. A low logic level on the preset or clear inputs will set o r reset th e outputs regardless of the logic levels o f th e o ther inputs. General Description This device contains tw o independent positive-edge-triggered D flip-flops w ith com plem entary o ut­

74LS74AN

Abstract: 54ls74aj 74ls74a ic
Contextual Info: S E M IC O N D U C T O R tm hold tim es are not violated. A low logic level on the preset or clear inputs will se t o r reset th e outputs regardless of the logic levels o f th e o ther inputs. General Description This device contains tw o independent positive-edge-triggered D flip-flops w ith com plem entary o ut­

Contextual Info: M M O T O R O L A SN54LS74A SN54LS74A D E S C R I P T I O N - The S N 5 4 L S / 7 4 L S 7 4 A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary

7474 D flip-flop circuit diagram

Abstract: 7474 D flip-flop 7474 LS 7474 ls 7474 74S74 74ls74a
Contextual Info: 7474, LS74A, S74 Signetjcs Flip-Flops Dual D-Type Flip-Flop Product Specification Logic Products DESCRIPTION T h e '7 4 is a dual positive edge-triggered D -type flip-flop featuring individual D ata, Clock, S e t and R eset inputs; also com ­ plem entary Q and Ü outputs.

7474 pin out diagram

Abstract: TTL 7474 7474 D flip-flop circuit diagram 74LS74A pin out configuration specifications 7474 7474 pin configuration 7474 7474 ttl Flip-Flops 7474 pin diagram of 7474
Contextual Info: 7474, LS74A, S74 Signetics Flip-Flops Dual D-Type Flip-Flop Product Specification Logic Products DESCRIPTION The '74 is a dual positive edge-triggered D-type flip-flop featuring individual Data, Clock, Set and Reset inputs; also com­ plementary Q and 5 outputs.

TTL 7474

Abstract: 7474 pin configuration 7474 D flip-flop circuit diagram pin diagram of 7474 7474 7474 PIN DIAGRAM LS74A 74574 7474 D flip-flop 8XC660
Contextual Info: Signetics 7474, LS74A, S74 Flip-Flops Dual D-Type Flip-Flop Product Specification Logic Products DESCRIPTION The '74 is a dual positive edge-triggered D-type flip-flop featuring individual Data, Clock, Set and Reset inputs; also com­ plementary Q and Q outputs.

TTL 7474

Abstract: 7474 pin out diagram 7474 D flip-flop circuit diagram 7474 7474 D flip-flop pin diagram of 7474 74LS74A pin out configuration 7474 j-k flip flop 7474 pin configuration pin configuration of d flip flip 7474
Contextual Info: 7474, LS74A, S74 Signetics Flip-Flops Dual D-Type Flip-Flop Product Specification Logic Products DESCRIPTION Th e '7 4 is a dual positive edge-triggered D-type flip-flop featuring individual Data, Clock, S et and R eset inputs; also com ­ plem entary Q and Q outputs.

74ls74ap

Abstract: M74LS74AP
Contextual Info: M IT S U B IS H I LSTTLs M74LS74AP DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOPS WITH SET AND RESET DESCRIPTION The M 7 4L S 74 A P is a semiconductor intergrated circuit PIN CONFIGURATION TOP VIEW containing 2 D-type positive edge-triggered flip -flo p circuits

74s74

Abstract: 54S74
Contextual Info: SN5474, SN54LS74A, SM54S74, SN7474, SN74LS74A, SN74S74 DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR DECEMBER 1983 - REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

rm 02 l 25 u

Contextual Info: AA M OTOROLA SN54LS74A SN54LS74A D E S C R IP T IO N - T h e S N 5 4 L S /7 4 L S 7 4 A d u a l e d g e -trig g e re d flip -flo p u tiliz e s S c h o ttk y TTL c ir c u itry to p ro d u c e h ig h speed D -ty p e flip -flo p s . E ach flip -flo p has in d iv id u a l cle a r and s e t in p u ts , a n d also c o m p le m e n ta ry

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

LS74A

Abstract: e142d SN54L74 SN54H74 SN5474 SN54LS74A SN54S74 SN74 SN74H74 SN74LS74A
Contextual Info: TYPES SN5474, SN54H74, SN54L74, SN54LS74A, SN54S74, DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLiÏ - f Lo P S W % P ^ E T AND C ^A R — _ _ . . . R E V IS E D D E C E M B E R 1 9 83 P ackage O ptions Include Both Plástic and C eram ic Chip Carriers in A dd itio n to Plastic

M74LS74AP

Abstract: 20-PIN
Contextual Info: M IT S U B IS H I LSTTLs M 7 4 L S 7 4 A P DUAL D -TY PE P O SIT IV E ED G E-TR IG G ER ED F LIP -FL O P S W ITH S E T AND R E S E T DESCRIPTION The M 7 4L S 74 A P is a semiconductor intergrated circuit PIN CONFIGURATION TOP VIEW containing 2 D-type positive edge-triggered flip -flo p circuits

SN5474

Abstract: SN54LS74A SN54S74 SN74 SN7474 SN74LS74A SN74S74 LS74A
Contextual Info: S N 5 474, S N 5 4 LS 74 A . S N 5 4S 74, S N 7474. S N 74 LS 74 A , S N 74S 74 D U A L D -T Y P E P O S IT IV E E D G E T R IG G E R ED F LIP -FL O P S W ITH P R E S E T A N D C LE A R DECEMBER 1983 - Package Options Include Plastic "'Small Outline" Packages, Ceramic Chip Carriers

74LS167

Abstract: F199 transistor 74LS382 74LS514 74LS76A 74LS183 transistor b1100 74LS204 74ls171 F199
Contextual Info: L F U J I T S U M ICR OELECTRO N ICS • 76C D 13 374T?b2 0003=170 0 ■ n Î-4 2 -1 1 -0 5 " m zæm F U JIT S U @iÆ<§ ñ w m ^ is s E s i GENERAL INFORMATION •. o f standard SSI's and M STs such as 7 4 L S series are prepared as macros called " F - M A C R G " in the library.

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411
Contextual Info: P L S -W S /H P MAX+PLUS II Programmable Logic Software for HP/Apollo Workstations Data Sheet September 1991, ver. 3 Features □ □ LI LI □ □ □ □ General Description Software support for Classic, M A X 5000, M A X 7000, and ST G E P L D s Runs on H ew lett Packard /A p o llo Series 3000, 3500, 4000, 4500, and

Altera lpm lib 8count

Abstract: 74LS74A EPF8452ALC84 FLEX8000 sram book 8count
Contextual Info: Introduction Viewlogic Powerview design tools and the Altera MAX+PLUS II development software together provide a complete and integrated programmable logic design environment for the Sun SPARCstation, HP 9000 Series 700, and IBM RISC System/6000 workstation platforms. This