74LVX112MTC Search Results

74LVX112

Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16
Contextual Info: 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs (Q, Q). These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse. Triggering occurs at a voltage level of

5555 FAIRCHILD optocoupler

Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
Contextual Info: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference

74LVX112

Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16
Contextual Info: Revised December 2003 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs (Q, Q). These devices are edge sensitive and

Contextual Info: Revised March 1999 SEMICONDUCTOR TM General Description The inputs tolerate voltages up to 7V allowing the interface of 5V system s to 3V system s. Features • Input voltage level translation from 5 V -3 V ■ Ideal fo r low pow er/low noise 3.3V applications

74LVX112

Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16 AD508
Contextual Info: S E M I C O N D U C T O R Revised March 1999 TM General Description either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The inputs tolerate voltages up to 7V allowing the interface

74LVX112

Abstract: 74LVX112M 74LVX112MTC 74LVX112MTCX 74LVX112MX 74LVX112SJ 74LVX112SJX LVX112 M16A M16D
Contextual Info: 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J K PRESET CLEAR and CLOCK and outputs (Q Q) These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse Triggering occurs at a voltage level

MC0628R

Abstract: 40373 74hc14n equivalent 4046 application note philips HCF4060BE HCF4017BE SN74121 application note MC74HC373DW mc0628 HCF4053BE
Contextual Info: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference

Contextual Info: A I R C H October 1996 I L D Revised March 1999 S E M [CONDUCTOR TM 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK

74LVX112

Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16
Contextual Info: Revised March 1999 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs (Q, Q). These devices are edge sensitive and

5555 FAIRCHILD optocoupler

Abstract: DM74LS75N MC74HC373DW 74hc14n equivalent HCF4060BE 40373 NC7S125M5X datasheet 14543 motorola 14049 CD40106BE
Contextual Info: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference

QMI519

Abstract: KEG3000D QMI-519 ra3906 GR828FC Kyocera mold compound Hitachi Datecode KE-G300 KE-G3000 Henkel
Contextual Info: Date Created: 1/28/2004 Date Issued: 3/2/2004 PCN # 20040411 DESIGN/PROCESS CHANGE NOTIFICATION - FINAL This is to inform you that a design and/or process change will be made to the following product s . This notification is for your information and concurrence.